drivers/accel/habanalabs/include/goya/asic_reg/tpc0_nrtr_masks.h
Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_nrtr_masks.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/accel/habanalabs/include/goya/asic_reg/tpc0_nrtr_masks.h- Extension
.h- Size
- 10349 bytes
- Lines
- 209
- Domain
- Driver Families
- Bucket
- drivers/accel
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef ASIC_REG_TPC0_NRTR_MASKS_H_
#define ASIC_REG_TPC0_NRTR_MASKS_H_
/*
*****************************************
* TPC0_NRTR (Prototype: IF_NRTR)
*****************************************
*/
/* TPC0_NRTR_HBW_MAX_CRED */
#define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
#define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
#define TPC0_NRTR_HBW_MAX_CRED_WR_RS_SHIFT 8
#define TPC0_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
#define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_SHIFT 16
#define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
#define TPC0_NRTR_HBW_MAX_CRED_RD_RS_SHIFT 24
#define TPC0_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
/* TPC0_NRTR_LBW_MAX_CRED */
#define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
#define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
#define TPC0_NRTR_LBW_MAX_CRED_WR_RS_SHIFT 8
#define TPC0_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
#define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_SHIFT 16
#define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
#define TPC0_NRTR_LBW_MAX_CRED_RD_RS_SHIFT 24
#define TPC0_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
/* TPC0_NRTR_DBG_E_ARB */
#define TPC0_NRTR_DBG_E_ARB_W_SHIFT 0
#define TPC0_NRTR_DBG_E_ARB_W_MASK 0x7
#define TPC0_NRTR_DBG_E_ARB_S_SHIFT 8
#define TPC0_NRTR_DBG_E_ARB_S_MASK 0x700
#define TPC0_NRTR_DBG_E_ARB_N_SHIFT 16
#define TPC0_NRTR_DBG_E_ARB_N_MASK 0x70000
#define TPC0_NRTR_DBG_E_ARB_L_SHIFT 24
#define TPC0_NRTR_DBG_E_ARB_L_MASK 0x7000000
/* TPC0_NRTR_DBG_W_ARB */
#define TPC0_NRTR_DBG_W_ARB_E_SHIFT 0
#define TPC0_NRTR_DBG_W_ARB_E_MASK 0x7
#define TPC0_NRTR_DBG_W_ARB_S_SHIFT 8
#define TPC0_NRTR_DBG_W_ARB_S_MASK 0x700
#define TPC0_NRTR_DBG_W_ARB_N_SHIFT 16
#define TPC0_NRTR_DBG_W_ARB_N_MASK 0x70000
#define TPC0_NRTR_DBG_W_ARB_L_SHIFT 24
#define TPC0_NRTR_DBG_W_ARB_L_MASK 0x7000000
/* TPC0_NRTR_DBG_N_ARB */
#define TPC0_NRTR_DBG_N_ARB_W_SHIFT 0
#define TPC0_NRTR_DBG_N_ARB_W_MASK 0x7
#define TPC0_NRTR_DBG_N_ARB_E_SHIFT 8
#define TPC0_NRTR_DBG_N_ARB_E_MASK 0x700
#define TPC0_NRTR_DBG_N_ARB_S_SHIFT 16
#define TPC0_NRTR_DBG_N_ARB_S_MASK 0x70000
#define TPC0_NRTR_DBG_N_ARB_L_SHIFT 24
#define TPC0_NRTR_DBG_N_ARB_L_MASK 0x7000000
/* TPC0_NRTR_DBG_S_ARB */
#define TPC0_NRTR_DBG_S_ARB_W_SHIFT 0
#define TPC0_NRTR_DBG_S_ARB_W_MASK 0x7
#define TPC0_NRTR_DBG_S_ARB_E_SHIFT 8
#define TPC0_NRTR_DBG_S_ARB_E_MASK 0x700
#define TPC0_NRTR_DBG_S_ARB_N_SHIFT 16
#define TPC0_NRTR_DBG_S_ARB_N_MASK 0x70000
#define TPC0_NRTR_DBG_S_ARB_L_SHIFT 24
#define TPC0_NRTR_DBG_S_ARB_L_MASK 0x7000000
/* TPC0_NRTR_DBG_L_ARB */
#define TPC0_NRTR_DBG_L_ARB_W_SHIFT 0
#define TPC0_NRTR_DBG_L_ARB_W_MASK 0x7
#define TPC0_NRTR_DBG_L_ARB_E_SHIFT 8
#define TPC0_NRTR_DBG_L_ARB_E_MASK 0x700
#define TPC0_NRTR_DBG_L_ARB_S_SHIFT 16
#define TPC0_NRTR_DBG_L_ARB_S_MASK 0x70000
#define TPC0_NRTR_DBG_L_ARB_N_SHIFT 24
#define TPC0_NRTR_DBG_L_ARB_N_MASK 0x7000000
/* TPC0_NRTR_DBG_E_ARB_MAX */
#define TPC0_NRTR_DBG_E_ARB_MAX_CREDIT_SHIFT 0
#define TPC0_NRTR_DBG_E_ARB_MAX_CREDIT_MASK 0x3F
/* TPC0_NRTR_DBG_W_ARB_MAX */
#define TPC0_NRTR_DBG_W_ARB_MAX_CREDIT_SHIFT 0
#define TPC0_NRTR_DBG_W_ARB_MAX_CREDIT_MASK 0x3F
/* TPC0_NRTR_DBG_N_ARB_MAX */
#define TPC0_NRTR_DBG_N_ARB_MAX_CREDIT_SHIFT 0
#define TPC0_NRTR_DBG_N_ARB_MAX_CREDIT_MASK 0x3FAnnotation
- Atlas domain: Driver Families / drivers/accel.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.