drivers/accel/habanalabs/include/goya/asic_reg/tpc0_nrtr_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/goya/asic_reg/tpc0_nrtr_regs.h

Extension

.h

Size

8564 bytes

Lines

227

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_TPC0_NRTR_REGS_H_
#define ASIC_REG_TPC0_NRTR_REGS_H_

/*
 *****************************************
 *   TPC0_NRTR (Prototype: IF_NRTR)
 *****************************************
 */

#define mmTPC0_NRTR_HBW_MAX_CRED                                     0xE00100

#define mmTPC0_NRTR_LBW_MAX_CRED                                     0xE00120

#define mmTPC0_NRTR_DBG_E_ARB                                        0xE00300

#define mmTPC0_NRTR_DBG_W_ARB                                        0xE00304

#define mmTPC0_NRTR_DBG_N_ARB                                        0xE00308

#define mmTPC0_NRTR_DBG_S_ARB                                        0xE0030C

#define mmTPC0_NRTR_DBG_L_ARB                                        0xE00310

#define mmTPC0_NRTR_DBG_E_ARB_MAX                                    0xE00320

#define mmTPC0_NRTR_DBG_W_ARB_MAX                                    0xE00324

#define mmTPC0_NRTR_DBG_N_ARB_MAX                                    0xE00328

#define mmTPC0_NRTR_DBG_S_ARB_MAX                                    0xE0032C

#define mmTPC0_NRTR_DBG_L_ARB_MAX                                    0xE00330

#define mmTPC0_NRTR_SPLIT_COEF_0                                     0xE00400

#define mmTPC0_NRTR_SPLIT_COEF_1                                     0xE00404

#define mmTPC0_NRTR_SPLIT_COEF_2                                     0xE00408

#define mmTPC0_NRTR_SPLIT_COEF_3                                     0xE0040C

#define mmTPC0_NRTR_SPLIT_COEF_4                                     0xE00410

#define mmTPC0_NRTR_SPLIT_COEF_5                                     0xE00414

#define mmTPC0_NRTR_SPLIT_COEF_6                                     0xE00418

#define mmTPC0_NRTR_SPLIT_COEF_7                                     0xE0041C

#define mmTPC0_NRTR_SPLIT_COEF_8                                     0xE00420

#define mmTPC0_NRTR_SPLIT_COEF_9                                     0xE00424

#define mmTPC0_NRTR_SPLIT_CFG                                        0xE00440

#define mmTPC0_NRTR_SPLIT_RD_SAT                                     0xE00444

#define mmTPC0_NRTR_SPLIT_RD_RST_TOKEN                               0xE00448

#define mmTPC0_NRTR_SPLIT_RD_TIMEOUT_0                               0xE0044C

#define mmTPC0_NRTR_SPLIT_RD_TIMEOUT_1                               0xE00450

#define mmTPC0_NRTR_SPLIT_WR_SAT                                     0xE00454

#define mmTPC0_NRTR_WPLIT_WR_TST_TOLEN                               0xE00458

#define mmTPC0_NRTR_SPLIT_WR_TIMEOUT_0                               0xE0045C

#define mmTPC0_NRTR_SPLIT_WR_TIMEOUT_1                               0xE00460

#define mmTPC0_NRTR_HBW_RANGE_HIT                                    0xE00470

#define mmTPC0_NRTR_HBW_RANGE_MASK_L_0                               0xE00480

#define mmTPC0_NRTR_HBW_RANGE_MASK_L_1                               0xE00484

#define mmTPC0_NRTR_HBW_RANGE_MASK_L_2                               0xE00488

#define mmTPC0_NRTR_HBW_RANGE_MASK_L_3                               0xE0048C

#define mmTPC0_NRTR_HBW_RANGE_MASK_L_4                               0xE00490

#define mmTPC0_NRTR_HBW_RANGE_MASK_L_5                               0xE00494

#define mmTPC0_NRTR_HBW_RANGE_MASK_L_6                               0xE00498

#define mmTPC0_NRTR_HBW_RANGE_MASK_L_7                               0xE0049C

#define mmTPC0_NRTR_HBW_RANGE_MASK_H_0                               0xE004A0

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.