drivers/accel/habanalabs/include/goya/asic_reg/tpc0_qm_masks.h
Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_qm_masks.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/accel/habanalabs/include/goya/asic_reg/tpc0_qm_masks.h- Extension
.h- Size
- 23893 bytes
- Lines
- 465
- Domain
- Driver Families
- Bucket
- drivers/accel
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef ASIC_REG_TPC0_QM_MASKS_H_
#define ASIC_REG_TPC0_QM_MASKS_H_
/*
*****************************************
* TPC0_QM (Prototype: QMAN)
*****************************************
*/
/* TPC0_QM_GLBL_CFG0 */
#define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
#define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0x1
#define TPC0_QM_GLBL_CFG0_CQF_EN_SHIFT 1
#define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x2
#define TPC0_QM_GLBL_CFG0_CP_EN_SHIFT 2
#define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x4
#define TPC0_QM_GLBL_CFG0_DMA_EN_SHIFT 3
#define TPC0_QM_GLBL_CFG0_DMA_EN_MASK 0x8
/* TPC0_QM_GLBL_CFG1 */
#define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
#define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0x1
#define TPC0_QM_GLBL_CFG1_CQF_STOP_SHIFT 1
#define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x2
#define TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT 2
#define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x4
#define TPC0_QM_GLBL_CFG1_DMA_STOP_SHIFT 3
#define TPC0_QM_GLBL_CFG1_DMA_STOP_MASK 0x8
#define TPC0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 8
#define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0x100
#define TPC0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 9
#define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x200
#define TPC0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 10
#define TPC0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x400
#define TPC0_QM_GLBL_CFG1_DMA_FLUSH_SHIFT 11
#define TPC0_QM_GLBL_CFG1_DMA_FLUSH_MASK 0x800
/* TPC0_QM_GLBL_PROT */
#define TPC0_QM_GLBL_PROT_PQF_PROT_SHIFT 0
#define TPC0_QM_GLBL_PROT_PQF_PROT_MASK 0x1
#define TPC0_QM_GLBL_PROT_CQF_PROT_SHIFT 1
#define TPC0_QM_GLBL_PROT_CQF_PROT_MASK 0x2
#define TPC0_QM_GLBL_PROT_CP_PROT_SHIFT 2
#define TPC0_QM_GLBL_PROT_CP_PROT_MASK 0x4
#define TPC0_QM_GLBL_PROT_DMA_PROT_SHIFT 3
#define TPC0_QM_GLBL_PROT_DMA_PROT_MASK 0x8
#define TPC0_QM_GLBL_PROT_PQF_ERR_PROT_SHIFT 4
#define TPC0_QM_GLBL_PROT_PQF_ERR_PROT_MASK 0x10
#define TPC0_QM_GLBL_PROT_CQF_ERR_PROT_SHIFT 5
#define TPC0_QM_GLBL_PROT_CQF_ERR_PROT_MASK 0x20
#define TPC0_QM_GLBL_PROT_CP_ERR_PROT_SHIFT 6
#define TPC0_QM_GLBL_PROT_CP_ERR_PROT_MASK 0x40
#define TPC0_QM_GLBL_PROT_DMA_ERR_PROT_SHIFT 7
#define TPC0_QM_GLBL_PROT_DMA_ERR_PROT_MASK 0x80
/* TPC0_QM_GLBL_ERR_CFG */
#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_INT_EN_SHIFT 0
#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_INT_EN_MASK 0x1
#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 1
#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0x2
#define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 2
#define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0x4
#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_INT_EN_SHIFT 3
#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_INT_EN_MASK 0x8
#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4
#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x10
#define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 5
#define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x20
#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_INT_EN_SHIFT 6
#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_INT_EN_MASK 0x40
#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 7
#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x80
#define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 8
#define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x100
#define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_INT_EN_SHIFT 9
#define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200
#define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT 10
#define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK 0x400
#define TPC0_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT 11
#define TPC0_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800
/* TPC0_QM_GLBL_ERR_ADDR_LO */
#define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0
#define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF
/* TPC0_QM_GLBL_ERR_ADDR_HI */
#define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0
#define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF
/* TPC0_QM_GLBL_ERR_WDATA */Annotation
- Atlas domain: Driver Families / drivers/accel.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.