drivers/accel/habanalabs/include/goya/asic_reg/tpc3_cmdq_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/goya/asic_reg/tpc3_cmdq_regs.h

Extension

.h

Size

5085 bytes

Lines

139

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_TPC3_CMDQ_REGS_H_
#define ASIC_REG_TPC3_CMDQ_REGS_H_

/*
 *****************************************
 *   TPC3_CMDQ (Prototype: CMDQ)
 *****************************************
 */

#define mmTPC3_CMDQ_GLBL_CFG0                                        0xEC9000

#define mmTPC3_CMDQ_GLBL_CFG1                                        0xEC9004

#define mmTPC3_CMDQ_GLBL_PROT                                        0xEC9008

#define mmTPC3_CMDQ_GLBL_ERR_CFG                                     0xEC900C

#define mmTPC3_CMDQ_GLBL_ERR_ADDR_LO                                 0xEC9010

#define mmTPC3_CMDQ_GLBL_ERR_ADDR_HI                                 0xEC9014

#define mmTPC3_CMDQ_GLBL_ERR_WDATA                                   0xEC9018

#define mmTPC3_CMDQ_GLBL_SECURE_PROPS                                0xEC901C

#define mmTPC3_CMDQ_GLBL_NON_SECURE_PROPS                            0xEC9020

#define mmTPC3_CMDQ_GLBL_STS0                                        0xEC9024

#define mmTPC3_CMDQ_GLBL_STS1                                        0xEC9028

#define mmTPC3_CMDQ_CQ_CFG0                                          0xEC90B0

#define mmTPC3_CMDQ_CQ_CFG1                                          0xEC90B4

#define mmTPC3_CMDQ_CQ_ARUSER                                        0xEC90B8

#define mmTPC3_CMDQ_CQ_PTR_LO                                        0xEC90C0

#define mmTPC3_CMDQ_CQ_PTR_HI                                        0xEC90C4

#define mmTPC3_CMDQ_CQ_TSIZE                                         0xEC90C8

#define mmTPC3_CMDQ_CQ_CTL                                           0xEC90CC

#define mmTPC3_CMDQ_CQ_PTR_LO_STS                                    0xEC90D4

#define mmTPC3_CMDQ_CQ_PTR_HI_STS                                    0xEC90D8

#define mmTPC3_CMDQ_CQ_TSIZE_STS                                     0xEC90DC

#define mmTPC3_CMDQ_CQ_CTL_STS                                       0xEC90E0

#define mmTPC3_CMDQ_CQ_STS0                                          0xEC90E4

#define mmTPC3_CMDQ_CQ_STS1                                          0xEC90E8

#define mmTPC3_CMDQ_CQ_RD_RATE_LIM_EN                                0xEC90F0

#define mmTPC3_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN                         0xEC90F4

#define mmTPC3_CMDQ_CQ_RD_RATE_LIM_SAT                               0xEC90F8

#define mmTPC3_CMDQ_CQ_RD_RATE_LIM_TOUT                              0xEC90FC

#define mmTPC3_CMDQ_CQ_IFIFO_CNT                                     0xEC9108

#define mmTPC3_CMDQ_CP_MSG_BASE0_ADDR_LO                             0xEC9120

#define mmTPC3_CMDQ_CP_MSG_BASE0_ADDR_HI                             0xEC9124

#define mmTPC3_CMDQ_CP_MSG_BASE1_ADDR_LO                             0xEC9128

#define mmTPC3_CMDQ_CP_MSG_BASE1_ADDR_HI                             0xEC912C

#define mmTPC3_CMDQ_CP_MSG_BASE2_ADDR_LO                             0xEC9130

#define mmTPC3_CMDQ_CP_MSG_BASE2_ADDR_HI                             0xEC9134

#define mmTPC3_CMDQ_CP_MSG_BASE3_ADDR_LO                             0xEC9138

#define mmTPC3_CMDQ_CP_MSG_BASE3_ADDR_HI                             0xEC913C

#define mmTPC3_CMDQ_CP_LDMA_TSIZE_OFFSET                             0xEC9140

#define mmTPC3_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET                       0xEC9144

#define mmTPC3_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET                       0xEC9148

#define mmTPC3_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET                       0xEC914C

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.