drivers/accel/habanalabs/include/goya/asic_reg/tpc5_cmdq_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/goya/asic_reg/tpc5_cmdq_regs.h

Extension

.h

Size

5085 bytes

Lines

139

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_TPC5_CMDQ_REGS_H_
#define ASIC_REG_TPC5_CMDQ_REGS_H_

/*
 *****************************************
 *   TPC5_CMDQ (Prototype: CMDQ)
 *****************************************
 */

#define mmTPC5_CMDQ_GLBL_CFG0                                        0xF49000

#define mmTPC5_CMDQ_GLBL_CFG1                                        0xF49004

#define mmTPC5_CMDQ_GLBL_PROT                                        0xF49008

#define mmTPC5_CMDQ_GLBL_ERR_CFG                                     0xF4900C

#define mmTPC5_CMDQ_GLBL_ERR_ADDR_LO                                 0xF49010

#define mmTPC5_CMDQ_GLBL_ERR_ADDR_HI                                 0xF49014

#define mmTPC5_CMDQ_GLBL_ERR_WDATA                                   0xF49018

#define mmTPC5_CMDQ_GLBL_SECURE_PROPS                                0xF4901C

#define mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS                            0xF49020

#define mmTPC5_CMDQ_GLBL_STS0                                        0xF49024

#define mmTPC5_CMDQ_GLBL_STS1                                        0xF49028

#define mmTPC5_CMDQ_CQ_CFG0                                          0xF490B0

#define mmTPC5_CMDQ_CQ_CFG1                                          0xF490B4

#define mmTPC5_CMDQ_CQ_ARUSER                                        0xF490B8

#define mmTPC5_CMDQ_CQ_PTR_LO                                        0xF490C0

#define mmTPC5_CMDQ_CQ_PTR_HI                                        0xF490C4

#define mmTPC5_CMDQ_CQ_TSIZE                                         0xF490C8

#define mmTPC5_CMDQ_CQ_CTL                                           0xF490CC

#define mmTPC5_CMDQ_CQ_PTR_LO_STS                                    0xF490D4

#define mmTPC5_CMDQ_CQ_PTR_HI_STS                                    0xF490D8

#define mmTPC5_CMDQ_CQ_TSIZE_STS                                     0xF490DC

#define mmTPC5_CMDQ_CQ_CTL_STS                                       0xF490E0

#define mmTPC5_CMDQ_CQ_STS0                                          0xF490E4

#define mmTPC5_CMDQ_CQ_STS1                                          0xF490E8

#define mmTPC5_CMDQ_CQ_RD_RATE_LIM_EN                                0xF490F0

#define mmTPC5_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN                         0xF490F4

#define mmTPC5_CMDQ_CQ_RD_RATE_LIM_SAT                               0xF490F8

#define mmTPC5_CMDQ_CQ_RD_RATE_LIM_TOUT                              0xF490FC

#define mmTPC5_CMDQ_CQ_IFIFO_CNT                                     0xF49108

#define mmTPC5_CMDQ_CP_MSG_BASE0_ADDR_LO                             0xF49120

#define mmTPC5_CMDQ_CP_MSG_BASE0_ADDR_HI                             0xF49124

#define mmTPC5_CMDQ_CP_MSG_BASE1_ADDR_LO                             0xF49128

#define mmTPC5_CMDQ_CP_MSG_BASE1_ADDR_HI                             0xF4912C

#define mmTPC5_CMDQ_CP_MSG_BASE2_ADDR_LO                             0xF49130

#define mmTPC5_CMDQ_CP_MSG_BASE2_ADDR_HI                             0xF49134

#define mmTPC5_CMDQ_CP_MSG_BASE3_ADDR_LO                             0xF49138

#define mmTPC5_CMDQ_CP_MSG_BASE3_ADDR_HI                             0xF4913C

#define mmTPC5_CMDQ_CP_LDMA_TSIZE_OFFSET                             0xF49140

#define mmTPC5_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET                       0xF49144

#define mmTPC5_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET                       0xF49148

#define mmTPC5_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET                       0xF4914C

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.