drivers/accel/habanalabs/include/goya/asic_reg/tpc5_qm_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/goya/asic_reg/tpc5_qm_regs.h

Extension

.h

Size

6657 bytes

Lines

179

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_TPC5_QM_REGS_H_
#define ASIC_REG_TPC5_QM_REGS_H_

/*
 *****************************************
 *   TPC5_QM (Prototype: QMAN)
 *****************************************
 */

#define mmTPC5_QM_GLBL_CFG0                                          0xF48000

#define mmTPC5_QM_GLBL_CFG1                                          0xF48004

#define mmTPC5_QM_GLBL_PROT                                          0xF48008

#define mmTPC5_QM_GLBL_ERR_CFG                                       0xF4800C

#define mmTPC5_QM_GLBL_ERR_ADDR_LO                                   0xF48010

#define mmTPC5_QM_GLBL_ERR_ADDR_HI                                   0xF48014

#define mmTPC5_QM_GLBL_ERR_WDATA                                     0xF48018

#define mmTPC5_QM_GLBL_SECURE_PROPS                                  0xF4801C

#define mmTPC5_QM_GLBL_NON_SECURE_PROPS                              0xF48020

#define mmTPC5_QM_GLBL_STS0                                          0xF48024

#define mmTPC5_QM_GLBL_STS1                                          0xF48028

#define mmTPC5_QM_PQ_BASE_LO                                         0xF48060

#define mmTPC5_QM_PQ_BASE_HI                                         0xF48064

#define mmTPC5_QM_PQ_SIZE                                            0xF48068

#define mmTPC5_QM_PQ_PI                                              0xF4806C

#define mmTPC5_QM_PQ_CI                                              0xF48070

#define mmTPC5_QM_PQ_CFG0                                            0xF48074

#define mmTPC5_QM_PQ_CFG1                                            0xF48078

#define mmTPC5_QM_PQ_ARUSER                                          0xF4807C

#define mmTPC5_QM_PQ_PUSH0                                           0xF48080

#define mmTPC5_QM_PQ_PUSH1                                           0xF48084

#define mmTPC5_QM_PQ_PUSH2                                           0xF48088

#define mmTPC5_QM_PQ_PUSH3                                           0xF4808C

#define mmTPC5_QM_PQ_STS0                                            0xF48090

#define mmTPC5_QM_PQ_STS1                                            0xF48094

#define mmTPC5_QM_PQ_RD_RATE_LIM_EN                                  0xF480A0

#define mmTPC5_QM_PQ_RD_RATE_LIM_RST_TOKEN                           0xF480A4

#define mmTPC5_QM_PQ_RD_RATE_LIM_SAT                                 0xF480A8

#define mmTPC5_QM_PQ_RD_RATE_LIM_TOUT                                0xF480AC

#define mmTPC5_QM_CQ_CFG0                                            0xF480B0

#define mmTPC5_QM_CQ_CFG1                                            0xF480B4

#define mmTPC5_QM_CQ_ARUSER                                          0xF480B8

#define mmTPC5_QM_CQ_PTR_LO                                          0xF480C0

#define mmTPC5_QM_CQ_PTR_HI                                          0xF480C4

#define mmTPC5_QM_CQ_TSIZE                                           0xF480C8

#define mmTPC5_QM_CQ_CTL                                             0xF480CC

#define mmTPC5_QM_CQ_PTR_LO_STS                                      0xF480D4

#define mmTPC5_QM_CQ_PTR_HI_STS                                      0xF480D8

#define mmTPC5_QM_CQ_TSIZE_STS                                       0xF480DC

#define mmTPC5_QM_CQ_CTL_STS                                         0xF480E0

#define mmTPC5_QM_CQ_STS0                                            0xF480E4

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.