drivers/accel/habanalabs/include/goya/asic_reg/tpc5_rtr_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/goya/asic_reg/tpc5_rtr_regs.h

Extension

.h

Size

12352 bytes

Lines

323

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_TPC5_RTR_REGS_H_
#define ASIC_REG_TPC5_RTR_REGS_H_

/*
 *****************************************
 *   TPC5_RTR (Prototype: TPC_RTR)
 *****************************************
 */

#define mmTPC5_RTR_HBW_RD_RQ_E_ARB                                   0xF40100

#define mmTPC5_RTR_HBW_RD_RQ_W_ARB                                   0xF40104

#define mmTPC5_RTR_HBW_RD_RQ_N_ARB                                   0xF40108

#define mmTPC5_RTR_HBW_RD_RQ_S_ARB                                   0xF4010C

#define mmTPC5_RTR_HBW_RD_RQ_L_ARB                                   0xF40110

#define mmTPC5_RTR_HBW_E_ARB_MAX                                     0xF40120

#define mmTPC5_RTR_HBW_W_ARB_MAX                                     0xF40124

#define mmTPC5_RTR_HBW_N_ARB_MAX                                     0xF40128

#define mmTPC5_RTR_HBW_S_ARB_MAX                                     0xF4012C

#define mmTPC5_RTR_HBW_L_ARB_MAX                                     0xF40130

#define mmTPC5_RTR_HBW_RD_RS_E_ARB                                   0xF40140

#define mmTPC5_RTR_HBW_RD_RS_W_ARB                                   0xF40144

#define mmTPC5_RTR_HBW_RD_RS_N_ARB                                   0xF40148

#define mmTPC5_RTR_HBW_RD_RS_S_ARB                                   0xF4014C

#define mmTPC5_RTR_HBW_RD_RS_L_ARB                                   0xF40150

#define mmTPC5_RTR_HBW_WR_RQ_E_ARB                                   0xF40170

#define mmTPC5_RTR_HBW_WR_RQ_W_ARB                                   0xF40174

#define mmTPC5_RTR_HBW_WR_RQ_N_ARB                                   0xF40178

#define mmTPC5_RTR_HBW_WR_RQ_S_ARB                                   0xF4017C

#define mmTPC5_RTR_HBW_WR_RQ_L_ARB                                   0xF40180

#define mmTPC5_RTR_HBW_WR_RS_E_ARB                                   0xF40190

#define mmTPC5_RTR_HBW_WR_RS_W_ARB                                   0xF40194

#define mmTPC5_RTR_HBW_WR_RS_N_ARB                                   0xF40198

#define mmTPC5_RTR_HBW_WR_RS_S_ARB                                   0xF4019C

#define mmTPC5_RTR_HBW_WR_RS_L_ARB                                   0xF401A0

#define mmTPC5_RTR_LBW_RD_RQ_E_ARB                                   0xF40200

#define mmTPC5_RTR_LBW_RD_RQ_W_ARB                                   0xF40204

#define mmTPC5_RTR_LBW_RD_RQ_N_ARB                                   0xF40208

#define mmTPC5_RTR_LBW_RD_RQ_S_ARB                                   0xF4020C

#define mmTPC5_RTR_LBW_RD_RQ_L_ARB                                   0xF40210

#define mmTPC5_RTR_LBW_E_ARB_MAX                                     0xF40220

#define mmTPC5_RTR_LBW_W_ARB_MAX                                     0xF40224

#define mmTPC5_RTR_LBW_N_ARB_MAX                                     0xF40228

#define mmTPC5_RTR_LBW_S_ARB_MAX                                     0xF4022C

#define mmTPC5_RTR_LBW_L_ARB_MAX                                     0xF40230

#define mmTPC5_RTR_LBW_RD_RS_E_ARB                                   0xF40250

#define mmTPC5_RTR_LBW_RD_RS_W_ARB                                   0xF40254

#define mmTPC5_RTR_LBW_RD_RS_N_ARB                                   0xF40258

#define mmTPC5_RTR_LBW_RD_RS_S_ARB                                   0xF4025C

#define mmTPC5_RTR_LBW_RD_RS_L_ARB                                   0xF40260

#define mmTPC5_RTR_LBW_WR_RQ_E_ARB                                   0xF40270

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.