drivers/accel/habanalabs/include/goya/asic_reg/tpc7_nrtr_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/goya/asic_reg/tpc7_nrtr_regs.h

Extension

.h

Size

8564 bytes

Lines

227

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_TPC7_NRTR_REGS_H_
#define ASIC_REG_TPC7_NRTR_REGS_H_

/*
 *****************************************
 *   TPC7_NRTR (Prototype: IF_NRTR)
 *****************************************
 */

#define mmTPC7_NRTR_HBW_MAX_CRED                                     0xFC0100

#define mmTPC7_NRTR_LBW_MAX_CRED                                     0xFC0120

#define mmTPC7_NRTR_DBG_E_ARB                                        0xFC0300

#define mmTPC7_NRTR_DBG_W_ARB                                        0xFC0304

#define mmTPC7_NRTR_DBG_N_ARB                                        0xFC0308

#define mmTPC7_NRTR_DBG_S_ARB                                        0xFC030C

#define mmTPC7_NRTR_DBG_L_ARB                                        0xFC0310

#define mmTPC7_NRTR_DBG_E_ARB_MAX                                    0xFC0320

#define mmTPC7_NRTR_DBG_W_ARB_MAX                                    0xFC0324

#define mmTPC7_NRTR_DBG_N_ARB_MAX                                    0xFC0328

#define mmTPC7_NRTR_DBG_S_ARB_MAX                                    0xFC032C

#define mmTPC7_NRTR_DBG_L_ARB_MAX                                    0xFC0330

#define mmTPC7_NRTR_SPLIT_COEF_0                                     0xFC0400

#define mmTPC7_NRTR_SPLIT_COEF_1                                     0xFC0404

#define mmTPC7_NRTR_SPLIT_COEF_2                                     0xFC0408

#define mmTPC7_NRTR_SPLIT_COEF_3                                     0xFC040C

#define mmTPC7_NRTR_SPLIT_COEF_4                                     0xFC0410

#define mmTPC7_NRTR_SPLIT_COEF_5                                     0xFC0414

#define mmTPC7_NRTR_SPLIT_COEF_6                                     0xFC0418

#define mmTPC7_NRTR_SPLIT_COEF_7                                     0xFC041C

#define mmTPC7_NRTR_SPLIT_COEF_8                                     0xFC0420

#define mmTPC7_NRTR_SPLIT_COEF_9                                     0xFC0424

#define mmTPC7_NRTR_SPLIT_CFG                                        0xFC0440

#define mmTPC7_NRTR_SPLIT_RD_SAT                                     0xFC0444

#define mmTPC7_NRTR_SPLIT_RD_RST_TOKEN                               0xFC0448

#define mmTPC7_NRTR_SPLIT_RD_TIMEOUT_0                               0xFC044C

#define mmTPC7_NRTR_SPLIT_RD_TIMEOUT_1                               0xFC0450

#define mmTPC7_NRTR_SPLIT_WR_SAT                                     0xFC0454

#define mmTPC7_NRTR_WPLIT_WR_TST_TOLEN                               0xFC0458

#define mmTPC7_NRTR_SPLIT_WR_TIMEOUT_0                               0xFC045C

#define mmTPC7_NRTR_SPLIT_WR_TIMEOUT_1                               0xFC0460

#define mmTPC7_NRTR_HBW_RANGE_HIT                                    0xFC0470

#define mmTPC7_NRTR_HBW_RANGE_MASK_L_0                               0xFC0480

#define mmTPC7_NRTR_HBW_RANGE_MASK_L_1                               0xFC0484

#define mmTPC7_NRTR_HBW_RANGE_MASK_L_2                               0xFC0488

#define mmTPC7_NRTR_HBW_RANGE_MASK_L_3                               0xFC048C

#define mmTPC7_NRTR_HBW_RANGE_MASK_L_4                               0xFC0490

#define mmTPC7_NRTR_HBW_RANGE_MASK_L_5                               0xFC0494

#define mmTPC7_NRTR_HBW_RANGE_MASK_L_6                               0xFC0498

#define mmTPC7_NRTR_HBW_RANGE_MASK_L_7                               0xFC049C

#define mmTPC7_NRTR_HBW_RANGE_MASK_H_0                               0xFC04A0

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.