drivers/accel/habanalabs/include/goya/goya_async_events.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/goya/goya_async_events.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/goya/goya_async_events.h
Extension
.h
Size
7347 bytes
Lines
201
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __GOYA_ASYNC_EVENTS_H_
#define __GOYA_ASYNC_EVENTS_H_

enum goya_async_event_id {
	GOYA_ASYNC_EVENT_ID_PCIE_CORE = 32,
	GOYA_ASYNC_EVENT_ID_PCIE_IF = 33,
	GOYA_ASYNC_EVENT_ID_PCIE_PHY = 34,
	GOYA_ASYNC_EVENT_ID_TPC0_ECC = 36,
	GOYA_ASYNC_EVENT_ID_TPC1_ECC = 39,
	GOYA_ASYNC_EVENT_ID_TPC2_ECC = 42,
	GOYA_ASYNC_EVENT_ID_TPC3_ECC = 45,
	GOYA_ASYNC_EVENT_ID_TPC4_ECC = 48,
	GOYA_ASYNC_EVENT_ID_TPC5_ECC = 51,
	GOYA_ASYNC_EVENT_ID_TPC6_ECC = 54,
	GOYA_ASYNC_EVENT_ID_TPC7_ECC = 57,
	GOYA_ASYNC_EVENT_ID_MME_ECC = 60,
	GOYA_ASYNC_EVENT_ID_MME_ECC_EXT = 61,
	GOYA_ASYNC_EVENT_ID_MMU_ECC = 63,
	GOYA_ASYNC_EVENT_ID_DMA_MACRO = 64,
	GOYA_ASYNC_EVENT_ID_DMA_ECC = 66,
	GOYA_ASYNC_EVENT_ID_DDR0_PARITY = 69,
	GOYA_ASYNC_EVENT_ID_DDR1_PARITY = 72,
	GOYA_ASYNC_EVENT_ID_CPU_IF_ECC = 75,
	GOYA_ASYNC_EVENT_ID_PSOC_MEM = 78,
	GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT = 79,
	GOYA_ASYNC_EVENT_ID_SRAM0 = 81,
	GOYA_ASYNC_EVENT_ID_SRAM1 = 82,
	GOYA_ASYNC_EVENT_ID_SRAM2 = 83,
	GOYA_ASYNC_EVENT_ID_SRAM3 = 84,
	GOYA_ASYNC_EVENT_ID_SRAM4 = 85,
	GOYA_ASYNC_EVENT_ID_SRAM5 = 86,
	GOYA_ASYNC_EVENT_ID_SRAM6 = 87,
	GOYA_ASYNC_EVENT_ID_SRAM7 = 88,
	GOYA_ASYNC_EVENT_ID_SRAM8 = 89,
	GOYA_ASYNC_EVENT_ID_SRAM9 = 90,
	GOYA_ASYNC_EVENT_ID_SRAM10 = 91,
	GOYA_ASYNC_EVENT_ID_SRAM11 = 92,
	GOYA_ASYNC_EVENT_ID_SRAM12 = 93,
	GOYA_ASYNC_EVENT_ID_SRAM13 = 94,
	GOYA_ASYNC_EVENT_ID_SRAM14 = 95,
	GOYA_ASYNC_EVENT_ID_SRAM15 = 96,
	GOYA_ASYNC_EVENT_ID_SRAM16 = 97,
	GOYA_ASYNC_EVENT_ID_SRAM17 = 98,
	GOYA_ASYNC_EVENT_ID_SRAM18 = 99,
	GOYA_ASYNC_EVENT_ID_SRAM19 = 100,
	GOYA_ASYNC_EVENT_ID_SRAM20 = 101,
	GOYA_ASYNC_EVENT_ID_SRAM21 = 102,
	GOYA_ASYNC_EVENT_ID_SRAM22 = 103,
	GOYA_ASYNC_EVENT_ID_SRAM23 = 104,
	GOYA_ASYNC_EVENT_ID_SRAM24 = 105,
	GOYA_ASYNC_EVENT_ID_SRAM25 = 106,
	GOYA_ASYNC_EVENT_ID_SRAM26 = 107,
	GOYA_ASYNC_EVENT_ID_SRAM27 = 108,
	GOYA_ASYNC_EVENT_ID_SRAM28 = 109,
	GOYA_ASYNC_EVENT_ID_SRAM29 = 110,
	GOYA_ASYNC_EVENT_ID_GIC500 = 112,
	GOYA_ASYNC_EVENT_ID_PCIE_DEC = 115,
	GOYA_ASYNC_EVENT_ID_TPC0_DEC = 117,
	GOYA_ASYNC_EVENT_ID_TPC1_DEC = 120,
	GOYA_ASYNC_EVENT_ID_TPC2_DEC = 123,
	GOYA_ASYNC_EVENT_ID_TPC3_DEC = 126,
	GOYA_ASYNC_EVENT_ID_TPC4_DEC = 129,
	GOYA_ASYNC_EVENT_ID_TPC5_DEC = 132,
	GOYA_ASYNC_EVENT_ID_TPC6_DEC = 135,
	GOYA_ASYNC_EVENT_ID_TPC7_DEC = 138,
	GOYA_ASYNC_EVENT_ID_AXI_ECC = 139,
	GOYA_ASYNC_EVENT_ID_L2_RAM_ECC = 140,
	GOYA_ASYNC_EVENT_ID_MME_WACS = 141,
	GOYA_ASYNC_EVENT_ID_MME_WACSD = 142,
	GOYA_ASYNC_EVENT_ID_PLL0 = 143,
	GOYA_ASYNC_EVENT_ID_PLL1 = 144,
	GOYA_ASYNC_EVENT_ID_PLL2 = 145,
	GOYA_ASYNC_EVENT_ID_PLL3 = 146,
	GOYA_ASYNC_EVENT_ID_PLL4 = 147,
	GOYA_ASYNC_EVENT_ID_PLL5 = 148,
	GOYA_ASYNC_EVENT_ID_PLL6 = 149,
	GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER = 155,
	GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC = 159,
	GOYA_ASYNC_EVENT_ID_PSOC = 160,
	GOYA_ASYNC_EVENT_ID_PCIE_FLR = 171,
	GOYA_ASYNC_EVENT_ID_PCIE_HOT_RESET = 172,
	GOYA_ASYNC_EVENT_ID_PCIE_PERST = 173,
	GOYA_ASYNC_EVENT_ID_PCIE_QID0_ENG0 = 174,
	GOYA_ASYNC_EVENT_ID_PCIE_QID0_ENG1 = 175,
	GOYA_ASYNC_EVENT_ID_PCIE_QID0_ENG2 = 176,
	GOYA_ASYNC_EVENT_ID_PCIE_QID0_ENG3 = 177,
	GOYA_ASYNC_EVENT_ID_PCIE_QID1_ENG0 = 178,
	GOYA_ASYNC_EVENT_ID_PCIE_QID1_ENG1 = 179,
	GOYA_ASYNC_EVENT_ID_PCIE_QID1_ENG2 = 180,
	GOYA_ASYNC_EVENT_ID_PCIE_QID1_ENG3 = 181,

Annotation

Implementation Notes