drivers/accel/habanalabs/include/goya/goya.h
Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/goya/goya.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/accel/habanalabs/include/goya/goya.h- Extension
.h- Size
- 854 bytes
- Lines
- 44
- Domain
- Driver Families
- Bucket
- drivers/accel
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef GOYA_H
#define GOYA_H
#define SRAM_CFG_BAR_ID 0
#define MSIX_BAR_ID 2
#define DDR_BAR_ID 4
#define CFG_BAR_SIZE 0x10000000ull /* 256MB */
#define MSIX_BAR_SIZE 0x1000ull /* 4KB */
#define CFG_BASE 0x7FFC000000ull
#define CFG_SIZE 0x4000000 /* 32MB CFG + 32MB DBG*/
#define SRAM_BASE_ADDR 0x7FF0000000ull
#define SRAM_SIZE 0x32A0000 /* 50.625MB */
#define DRAM_PHYS_BASE 0x0ull
#define HOST_PHYS_BASE 0x8000000000ull /* 0.5TB */
#define HOST_PHYS_SIZE 0x1000000000000ull /* 0.25PB (48 bits) */
#define GOYA_MSIX_ENTRIES 8
#define QMAN_PQ_ENTRY_SIZE 16 /* Bytes */
#define MAX_ASID 2
#define PROT_BITS_OFFS 0xF80
#define DMA_MAX_NUM 5
#define TPC_MAX_NUM 8
#define MME_MAX_NUM 1
#endif /* GOYA_H */
Annotation
- Atlas domain: Driver Families / drivers/accel.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.