drivers/accel/ivpu/ivpu_hw_btrs.c

Source file repositories/reference/linux-study-clean/drivers/accel/ivpu/ivpu_hw_btrs.c

File Facts

System
Linux kernel
Corpus path
drivers/accel/ivpu/ivpu_hw_btrs.c
Extension
.c
Size
28646 bytes
Lines
972
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct wp_request {
	u16 min;
	u16 max;
	u16 target;
	u16 cfg;
	u16 epp;
	u16 cdyn;
};

static void wp_request_mtl(struct ivpu_device *vdev, struct wp_request *wp)
{
	u32 val;

	val = REGB_RD32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0);
	val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0, MIN_RATIO, wp->min, val);
	val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0, MAX_RATIO, wp->max, val);
	REGB_WR32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0, val);

	val = REGB_RD32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1);
	val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1, TARGET_RATIO, wp->target, val);
	val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1, EPP, PLL_EPP_DEFAULT, val);
	REGB_WR32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1, val);

	val = REGB_RD32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2);
	val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2, CONFIG, wp->cfg, val);
	REGB_WR32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2, val);

	val = REGB_RD32(VPU_HW_BTRS_MTL_WP_REQ_CMD);
	val = REG_SET_FLD(VPU_HW_BTRS_MTL_WP_REQ_CMD, SEND, val);
	REGB_WR32(VPU_HW_BTRS_MTL_WP_REQ_CMD, val);
}

static void wp_request_lnl(struct ivpu_device *vdev, struct wp_request *wp)
{
	u32 val;

	val = REGB_RD32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0);
	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0, MIN_RATIO, wp->min, val);
	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0, MAX_RATIO, wp->max, val);
	REGB_WR32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0, val);

	val = REGB_RD32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1);
	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, TARGET_RATIO, wp->target, val);
	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, EPP, wp->epp, val);
	REGB_WR32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, val);

	val = REGB_RD32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2);
	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, CONFIG, wp->cfg, val);
	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, CDYN, wp->cdyn, val);
	REGB_WR32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, val);

	val = REGB_RD32(VPU_HW_BTRS_LNL_WP_REQ_CMD);
	val = REG_SET_FLD(VPU_HW_BTRS_LNL_WP_REQ_CMD, SEND, val);
	REGB_WR32(VPU_HW_BTRS_LNL_WP_REQ_CMD, val);
}

static void wp_request(struct ivpu_device *vdev, struct wp_request *wp)
{
	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
		wp_request_mtl(vdev, wp);
	else
		wp_request_lnl(vdev, wp);
}

static int wp_request_send(struct ivpu_device *vdev, struct wp_request *wp)
{
	int ret;

	ret = wp_request_sync(vdev);
	if (ret) {
		ivpu_err(vdev, "Failed to sync before workpoint request: %d\n", ret);
		return ret;
	}

	wp_request(vdev, wp);

	ret = wp_request_sync(vdev);
	if (ret)
		ivpu_err(vdev, "Failed to sync after workpoint request: %d\n", ret);

	return ret;
}

static void prepare_wp_request(struct ivpu_device *vdev, struct wp_request *wp, bool enable)
{
	struct ivpu_hw_info *hw = vdev->hw;

	wp->min = hw->pll.min_ratio;
	wp->max = hw->pll.max_ratio;

Annotation

Implementation Notes