drivers/accel/ivpu/ivpu_mmu.c
Source file repositories/reference/linux-study-clean/drivers/accel/ivpu/ivpu_mmu.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/accel/ivpu/ivpu_mmu.c- Extension
.c- Size
- 29942 bytes
- Lines
- 1031
- Domain
- Driver Families
- Bucket
- drivers/accel
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/circ_buf.hlinux/highmem.hivpu_drv.hivpu_hw.hivpu_hw_reg_io.hivpu_mmu.hivpu_mmu_context.hivpu_pm.h
Detected Declarations
function Copyrightfunction ivpu_mmu_config_checkfunction ivpu_mmu_cdtab_allocfunction ivpu_mmu_strtab_allocfunction ivpu_mmu_cmdq_allocfunction ivpu_mmu_evtq_allocfunction ivpu_mmu_structs_allocfunction ivpu_mmu_reg_write_cr0function ivpu_mmu_reg_write_irq_ctrlfunction ivpu_mmu_irqs_setupfunction ivpu_mmu_cmdq_wait_for_consfunction ivpu_mmu_queue_is_fullfunction ivpu_mmu_queue_is_emptyfunction ivpu_mmu_cmdq_cmd_writefunction ivpu_mmu_cmdq_syncfunction ivpu_mmu_cmdq_write_cfgi_allfunction ivpu_mmu_cmdq_write_tlbi_nh_asidfunction ivpu_mmu_cmdq_write_tlbi_nsnh_allfunction ivpu_mmu_resetfunction ivpu_mmu_strtab_link_cdfunction ivpu_mmu_strtab_initfunction ivpu_mmu_invalidate_tlbfunction ivpu_mmu_cdtab_entry_setfunction ivpu_mmu_initfunction ivpu_mmu_enablefunction ivpu_mmu_disablefunction ivpu_mmu_dump_eventfunction ivpu_mmu_evtq_setfunction ivpu_mmu_evtq_enablefunction ivpu_mmu_evtq_disablefunction ivpu_mmu_discard_eventsfunction ivpu_mmu_disable_ssid_eventsfunction ivpu_mmu_irq_evtq_handlerfunction ivpu_mmu_evtq_dumpfunction ivpu_mmu_irq_gerr_handlerfunction ivpu_mmu_cd_setfunction ivpu_mmu_cd_clear
Annotated Snippet
if (file_priv) {
if (!READ_ONCE(file_priv->has_mmu_faults)) {
atomic_set(&vdev->faults_detected, 1);
ivpu_mmu_dump_event(vdev, event);
WRITE_ONCE(file_priv->has_mmu_faults, true);
}
}
}
queue_work(system_percpu_wq, &vdev->context_abort_work);
}
void ivpu_mmu_evtq_dump(struct ivpu_device *vdev)
{
u32 *event;
while ((event = ivpu_mmu_get_event(vdev)) != NULL)
ivpu_mmu_dump_event(vdev, event);
}
void ivpu_mmu_irq_gerr_handler(struct ivpu_device *vdev)
{
u32 gerror_val, gerrorn_val, active;
ivpu_dbg(vdev, IRQ, "MMU error\n");
gerror_val = REGV_RD32(IVPU_MMU_REG_GERROR);
gerrorn_val = REGV_RD32(IVPU_MMU_REG_GERRORN);
active = gerror_val ^ gerrorn_val;
if (!(active & IVPU_MMU_GERROR_ERR_MASK))
return;
if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, MSI_ABT, active))
ivpu_warn_ratelimited(vdev, "MMU MSI ABT write aborted\n");
if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, MSI_PRIQ_ABT, active))
ivpu_warn_ratelimited(vdev, "MMU PRIQ MSI ABT write aborted\n");
if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, MSI_EVTQ_ABT, active))
ivpu_warn_ratelimited(vdev, "MMU EVTQ MSI ABT write aborted\n");
if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, MSI_CMDQ_ABT, active))
ivpu_warn_ratelimited(vdev, "MMU CMDQ MSI ABT write aborted\n");
if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, PRIQ_ABT, active))
ivpu_err_ratelimited(vdev, "MMU PRIQ write aborted\n");
if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, EVTQ_ABT, active))
ivpu_err_ratelimited(vdev, "MMU EVTQ write aborted\n");
if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, CMDQ, active))
ivpu_err_ratelimited(vdev, "MMU CMDQ write aborted\n");
REGV_WR32(IVPU_MMU_REG_GERRORN, gerror_val);
}
int ivpu_mmu_cd_set(struct ivpu_device *vdev, int ssid, struct ivpu_mmu_pgtable *pgtable)
{
return ivpu_mmu_cdtab_entry_set(vdev, ssid, pgtable->pgd_dma, true);
}
void ivpu_mmu_cd_clear(struct ivpu_device *vdev, int ssid)
{
ivpu_mmu_cdtab_entry_set(vdev, ssid, 0, false);
}
Annotation
- Immediate include surface: `linux/circ_buf.h`, `linux/highmem.h`, `ivpu_drv.h`, `ivpu_hw.h`, `ivpu_hw_reg_io.h`, `ivpu_mmu.h`, `ivpu_mmu_context.h`, `ivpu_pm.h`.
- Detected declarations: `function Copyright`, `function ivpu_mmu_config_check`, `function ivpu_mmu_cdtab_alloc`, `function ivpu_mmu_strtab_alloc`, `function ivpu_mmu_cmdq_alloc`, `function ivpu_mmu_evtq_alloc`, `function ivpu_mmu_structs_alloc`, `function ivpu_mmu_reg_write_cr0`, `function ivpu_mmu_reg_write_irq_ctrl`, `function ivpu_mmu_irqs_setup`.
- Atlas domain: Driver Families / drivers/accel.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.