drivers/accel/ivpu/Makefile

File Facts

System

Linux kernel

Corpus path

drivers/accel/ivpu/Makefile

Extension

[no extension]

Size

616 bytes

Lines

31

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: build/configuration rule

Status

atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

# SPDX-License-Identifier: GPL-2.0-only
# Copyright (C) 2023-2024 Intel Corporation

intel_vpu-y := \
	ivpu_drv.o \
	ivpu_fw.o \
	ivpu_fw_log.o \
	ivpu_gem.o \
	ivpu_gem_userptr.o \
	ivpu_hw.o \
	ivpu_hw_btrs.o \
	ivpu_hw_ip.o \
	ivpu_ipc.o \
	ivpu_job.o \
	ivpu_jsm_msg.o \
	ivpu_mmu.o \
	ivpu_mmu_context.o \
	ivpu_ms.o \
	ivpu_pm.o \
	ivpu_sysfs.o \
	ivpu_trace_points.o

intel_vpu-$(CONFIG_DEBUG_FS) += ivpu_debugfs.o
intel_vpu-$(CONFIG_DEV_COREDUMP) += ivpu_coredump.o

obj-$(CONFIG_DRM_ACCEL_IVPU) += intel_vpu.o

subdir-ccflags-$(CONFIG_DRM_ACCEL_IVPU_DEBUG) += -DDEBUG

CFLAGS_ivpu_trace_points.o = -I$(src)

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.