drivers/accel/rocket/rocket_registers.h

Source file repositories/reference/linux-study-clean/drivers/accel/rocket/rocket_registers.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/rocket/rocket_registers.h
Extension
.h
Size
193636 bytes
Lines
4405
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __ROCKET_REGISTERS_XML__
#define __ROCKET_REGISTERS_XML__

/* Autogenerated file, DO NOT EDIT manually!

This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
http://gitlab.freedesktop.org/mesa/mesa/
git clone https://gitlab.freedesktop.org/mesa/mesa.git

The rules-ng-ng source files this header was generated from are:

- /home/tomeu/src/mesa/src/gallium/drivers/rocket/registers.xml (  60076 bytes, from Wed Jun 12 10:02:25 2024)

Copyright (C) 2024-2025 by the following authors:
- Tomeu Vizoso <tomeu@tomeuvizoso.net>
*/

#define REG_PC_VERSION						0x00000000
#define PC_VERSION_VERSION__MASK				0xffffffff
#define PC_VERSION_VERSION__SHIFT				0
static inline uint32_t PC_VERSION_VERSION(uint32_t val)
{
	return ((val) << PC_VERSION_VERSION__SHIFT) & PC_VERSION_VERSION__MASK;
}

#define REG_PC_VERSION_NUM					0x00000004
#define PC_VERSION_NUM_VERSION_NUM__MASK			0xffffffff
#define PC_VERSION_NUM_VERSION_NUM__SHIFT			0
static inline uint32_t PC_VERSION_NUM_VERSION_NUM(uint32_t val)
{
	return ((val) << PC_VERSION_NUM_VERSION_NUM__SHIFT) & PC_VERSION_NUM_VERSION_NUM__MASK;
}

#define REG_PC_OPERATION_ENABLE					0x00000008
#define PC_OPERATION_ENABLE_RESERVED_0__MASK			0xfffffffe
#define PC_OPERATION_ENABLE_RESERVED_0__SHIFT			1
static inline uint32_t PC_OPERATION_ENABLE_RESERVED_0(uint32_t val)
{
	return ((val) << PC_OPERATION_ENABLE_RESERVED_0__SHIFT) & PC_OPERATION_ENABLE_RESERVED_0__MASK;
}
#define PC_OPERATION_ENABLE_OP_EN__MASK				0x00000001
#define PC_OPERATION_ENABLE_OP_EN__SHIFT			0
static inline uint32_t PC_OPERATION_ENABLE_OP_EN(uint32_t val)
{
	return ((val) << PC_OPERATION_ENABLE_OP_EN__SHIFT) & PC_OPERATION_ENABLE_OP_EN__MASK;
}

#define REG_PC_BASE_ADDRESS					0x00000010
#define PC_BASE_ADDRESS_PC_SOURCE_ADDR__MASK			0xfffffff0
#define PC_BASE_ADDRESS_PC_SOURCE_ADDR__SHIFT			4
static inline uint32_t PC_BASE_ADDRESS_PC_SOURCE_ADDR(uint32_t val)
{
	return ((val) << PC_BASE_ADDRESS_PC_SOURCE_ADDR__SHIFT) & PC_BASE_ADDRESS_PC_SOURCE_ADDR__MASK;
}
#define PC_BASE_ADDRESS_RESERVED_0__MASK			0x0000000e
#define PC_BASE_ADDRESS_RESERVED_0__SHIFT			1
static inline uint32_t PC_BASE_ADDRESS_RESERVED_0(uint32_t val)
{
	return ((val) << PC_BASE_ADDRESS_RESERVED_0__SHIFT) & PC_BASE_ADDRESS_RESERVED_0__MASK;
}
#define PC_BASE_ADDRESS_PC_SEL__MASK				0x00000001
#define PC_BASE_ADDRESS_PC_SEL__SHIFT				0
static inline uint32_t PC_BASE_ADDRESS_PC_SEL(uint32_t val)
{
	return ((val) << PC_BASE_ADDRESS_PC_SEL__SHIFT) & PC_BASE_ADDRESS_PC_SEL__MASK;
}

#define REG_PC_REGISTER_AMOUNTS					0x00000014
#define PC_REGISTER_AMOUNTS_RESERVED_0__MASK			0xffff0000
#define PC_REGISTER_AMOUNTS_RESERVED_0__SHIFT			16
static inline uint32_t PC_REGISTER_AMOUNTS_RESERVED_0(uint32_t val)
{
	return ((val) << PC_REGISTER_AMOUNTS_RESERVED_0__SHIFT) & PC_REGISTER_AMOUNTS_RESERVED_0__MASK;
}
#define PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT__MASK		0x0000ffff
#define PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT__SHIFT		0
static inline uint32_t PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT(uint32_t val)
{
	return ((val) << PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT__SHIFT) & PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT__MASK;
}

#define REG_PC_INTERRUPT_MASK					0x00000020
#define PC_INTERRUPT_MASK_RESERVED_0__MASK			0xffffc000
#define PC_INTERRUPT_MASK_RESERVED_0__SHIFT			14
static inline uint32_t PC_INTERRUPT_MASK_RESERVED_0(uint32_t val)
{
	return ((val) << PC_INTERRUPT_MASK_RESERVED_0__SHIFT) & PC_INTERRUPT_MASK_RESERVED_0__MASK;
}
#define PC_INTERRUPT_MASK_DMA_WRITE_ERROR			0x00002000
#define PC_INTERRUPT_MASK_DMA_READ_ERROR			0x00001000

Annotation

Implementation Notes