drivers/acpi/pmic/intel_pmic_bxtwc.c
Source file repositories/reference/linux-study-clean/drivers/acpi/pmic/intel_pmic_bxtwc.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/acpi/pmic/intel_pmic_bxtwc.c- Extension
.c- Size
- 7907 bytes
- Lines
- 409
- Domain
- Driver Families
- Bucket
- drivers/acpi
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/init.hlinux/acpi.hlinux/mfd/intel_soc_pmic.hlinux/regmap.hlinux/platform_device.hintel_pmic.h
Detected Declarations
function intel_bxtwc_pmic_get_powerfunction intel_bxtwc_pmic_update_powerfunction intel_bxtwc_pmic_get_raw_tempfunction intel_bxtwc_pmic_update_auxfunction intel_bxtwc_pmic_get_policyfunction intel_bxtwc_pmic_update_policyfunction intel_bxtwc_pmic_opregion_probe
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/*
* Intel BXT WhiskeyCove PMIC operation region driver
*
* Copyright (C) 2015 Intel Corporation. All rights reserved.
*/
#include <linux/init.h>
#include <linux/acpi.h>
#include <linux/mfd/intel_soc_pmic.h>
#include <linux/regmap.h>
#include <linux/platform_device.h>
#include "intel_pmic.h"
#define WHISKEY_COVE_ALRT_HIGH_BIT_MASK 0x0F
#define WHISKEY_COVE_ADC_HIGH_BIT(x) (((x & 0x0F) << 8))
#define WHISKEY_COVE_ADC_CURSRC(x) (((x & 0xF0) >> 4))
#define VR_MODE_DISABLED 0
#define VR_MODE_AUTO BIT(0)
#define VR_MODE_NORMAL BIT(1)
#define VR_MODE_SWITCH BIT(2)
#define VR_MODE_ECO (BIT(0)|BIT(1))
#define VSWITCH2_OUTPUT BIT(5)
#define VSWITCH1_OUTPUT BIT(4)
#define VUSBPHY_CHARGE BIT(1)
static const struct pmic_table power_table[] = {
{
.address = 0x0,
.reg = 0x63,
.bit = VR_MODE_AUTO,
}, /* VDD1 -> VDD1CNT */
{
.address = 0x04,
.reg = 0x65,
.bit = VR_MODE_AUTO,
}, /* VDD2 -> VDD2CNT */
{
.address = 0x08,
.reg = 0x67,
.bit = VR_MODE_AUTO,
}, /* VDD3 -> VDD3CNT */
{
.address = 0x0c,
.reg = 0x6d,
.bit = VR_MODE_AUTO,
}, /* VLFX -> VFLEXCNT */
{
.address = 0x10,
.reg = 0x6f,
.bit = VR_MODE_NORMAL,
}, /* VP1A -> VPROG1ACNT */
{
.address = 0x14,
.reg = 0x70,
.bit = VR_MODE_NORMAL,
}, /* VP1B -> VPROG1BCNT */
{
.address = 0x18,
.reg = 0x71,
.bit = VR_MODE_NORMAL,
}, /* VP1C -> VPROG1CCNT */
{
.address = 0x1c,
.reg = 0x72,
.bit = VR_MODE_NORMAL,
}, /* VP1D -> VPROG1DCNT */
{
.address = 0x20,
.reg = 0x73,
.bit = VR_MODE_NORMAL,
}, /* VP2A -> VPROG2ACNT */
{
.address = 0x24,
.reg = 0x74,
.bit = VR_MODE_NORMAL,
}, /* VP2B -> VPROG2BCNT */
{
.address = 0x28,
.reg = 0x75,
.bit = VR_MODE_NORMAL,
}, /* VP2C -> VPROG2CCNT */
{
.address = 0x2c,
.reg = 0x76,
.bit = VR_MODE_NORMAL,
}, /* VP3A -> VPROG3ACNT */
{
.address = 0x30,
.reg = 0x77,
Annotation
- Immediate include surface: `linux/init.h`, `linux/acpi.h`, `linux/mfd/intel_soc_pmic.h`, `linux/regmap.h`, `linux/platform_device.h`, `intel_pmic.h`.
- Detected declarations: `function intel_bxtwc_pmic_get_power`, `function intel_bxtwc_pmic_update_power`, `function intel_bxtwc_pmic_get_raw_temp`, `function intel_bxtwc_pmic_update_aux`, `function intel_bxtwc_pmic_get_policy`, `function intel_bxtwc_pmic_update_policy`, `function intel_bxtwc_pmic_opregion_probe`.
- Atlas domain: Driver Families / drivers/acpi.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.