drivers/ata/sata_mv.c
Source file repositories/reference/linux-study-clean/drivers/ata/sata_mv.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/ata/sata_mv.c- Extension
.c- Size
- 125593 bytes
- Lines
- 4496
- Domain
- Driver Families
- Bucket
- drivers/ata
- Inferred role
- Driver Families: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/module.hlinux/pci.hlinux/init.hlinux/blkdev.hlinux/delay.hlinux/interrupt.hlinux/dmapool.hlinux/dma-mapping.hlinux/device.hlinux/clk.hlinux/phy/phy.hlinux/platform_device.hlinux/ata_platform.hlinux/mbus.hlinux/bitops.hlinux/gfp.hlinux/of.hlinux/of_irq.hscsi/scsi_host.hscsi/scsi_cmnd.hscsi/scsi_device.hlinux/libata.h
Detected Declarations
struct mv_crqbstruct mv_crqb_iiestruct mv_crpbstruct mv_sgstruct mv_cached_regsstruct mv_port_privstruct mv_port_signalstruct mv_host_privstruct mv_hw_opsenum chip_typefunction writelflfunction mv_hc_from_portfunction mv_hardport_from_portfunction mv_get_hc_countfunction mv_save_cached_regsfunction mv_write_cached_regfunction mv_set_edma_ptrsfunction mv_write_main_irq_maskfunction mv_set_main_irq_maskfunction mv_enable_port_irqsfunction mv_clear_and_enable_port_irqsfunction mv_set_irq_coalescingfunction mv_start_edmafunction mv_wait_for_edma_empty_idlefunction mv_stop_edma_enginefunction mv_stop_edmafunction mv_dump_memfunction mv_dump_pci_cfgfunction mv_dump_all_regsfunction mv_scr_offsetfunction mv_scr_readfunction mv_scr_writefunction mv6_dev_configfunction mv_qc_deferfunction modefunction mv_config_fbsfunction mv_60x1_errata_sata25function mv_bmdma_enable_iiefunction mv_soc_led_blink_enablefunction mv_soc_led_blink_disablefunction mv_edma_cfgfunction mv_port_free_dma_memfunction mv_port_startfunction mv_port_stopfunction mv_fill_sgfunction mv_crqb_pack_cmdfunction mv_sff_irq_clearfunction mv_check_atapi_dma
Annotated Snippet
static struct pci_driver mv_pci_driver = {
.name = DRV_NAME,
.id_table = mv_pci_tbl,
.probe = mv_pci_init_one,
.remove = ata_pci_remove_one,
#ifdef CONFIG_PM_SLEEP
.suspend = ata_pci_device_suspend,
.resume = mv_pci_device_resume,
#endif
};
MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
/**
* mv_print_info - Dump key info to kernel log for perusal.
* @host: ATA host to print info about
*
* FIXME: complete this.
*
* LOCKING:
* Inherited from caller.
*/
static void mv_print_info(struct ata_host *host)
{
struct pci_dev *pdev = to_pci_dev(host->dev);
struct mv_host_priv *hpriv = host->private_data;
u8 scc;
const char *scc_s, *gen;
/* Use this to determine the HW stepping of the chip so we know
* what errata to workaround
*/
pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
if (scc == 0)
scc_s = "SCSI";
else if (scc == 0x01)
scc_s = "RAID";
else
scc_s = "?";
if (IS_GEN_I(hpriv))
gen = "I";
else if (IS_GEN_II(hpriv))
gen = "II";
else if (IS_GEN_IIE(hpriv))
gen = "IIE";
else
gen = "?";
dev_info(&pdev->dev, "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
}
/**
* mv_pci_init_one - handle a positive probe of a PCI Marvell host
* @pdev: PCI device found
* @ent: PCI device ID entry for the matched host
*
* LOCKING:
* Inherited from caller.
*/
static int mv_pci_init_one(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
unsigned int board_idx = (unsigned int)ent->driver_data;
const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
struct ata_host *host;
struct mv_host_priv *hpriv;
int n_ports, port, rc;
ata_print_version_once(&pdev->dev, DRV_VERSION);
/* allocate host */
n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
if (!host || !hpriv)
return -ENOMEM;
host->private_data = hpriv;
hpriv->n_ports = n_ports;
hpriv->board_idx = board_idx;
/* acquire resources */
rc = pcim_enable_device(pdev);
if (rc)
return rc;
rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/module.h`, `linux/pci.h`, `linux/init.h`, `linux/blkdev.h`, `linux/delay.h`, `linux/interrupt.h`, `linux/dmapool.h`.
- Detected declarations: `struct mv_crqb`, `struct mv_crqb_iie`, `struct mv_crpb`, `struct mv_sg`, `struct mv_cached_regs`, `struct mv_port_priv`, `struct mv_port_signal`, `struct mv_host_priv`, `struct mv_hw_ops`, `enum chip_type`.
- Atlas domain: Driver Families / drivers/ata.
- Implementation status: pattern implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.