drivers/ata/sata_rcar.c

Source file repositories/reference/linux-study-clean/drivers/ata/sata_rcar.c

File Facts

System
Linux kernel
Corpus path
drivers/ata/sata_rcar.c
Extension
.c
Size
26553 bytes
Lines
1027
Domain
Driver Families
Bucket
drivers/ata
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct sata_rcar_priv {
	void __iomem *base;
	u32 sataint_mask;
	enum sata_rcar_type type;
};

static void sata_rcar_gen1_phy_preinit(struct sata_rcar_priv *priv)
{
	void __iomem *base = priv->base;

	/* idle state */
	iowrite32(0, base + SATAPHYADDR_REG);
	/* reset */
	iowrite32(SATAPHYRESET_PHYRST, base + SATAPHYRESET_REG);
	udelay(10);
	/* deassert reset */
	iowrite32(0, base + SATAPHYRESET_REG);
}

static void sata_rcar_gen1_phy_write(struct sata_rcar_priv *priv, u16 reg,
				     u32 val, int group)
{
	void __iomem *base = priv->base;
	int timeout;

	/* deassert reset */
	iowrite32(0, base + SATAPHYRESET_REG);
	/* lane 1 */
	iowrite32(SATAPHYACCEN_PHYLANE, base + SATAPHYACCEN_REG);
	/* write phy register value */
	iowrite32(val, base + SATAPHYWDATA_REG);
	/* set register group */
	if (group)
		reg |= SATAPHYADDR_PHYRATEMODE;
	/* write command */
	iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, base + SATAPHYADDR_REG);
	/* wait for ack */
	for (timeout = 0; timeout < 100; timeout++) {
		val = ioread32(base + SATAPHYACK_REG);
		if (val & SATAPHYACK_PHYACK)
			break;
	}
	if (timeout >= 100)
		pr_err("%s timeout\n", __func__);
	/* idle state */
	iowrite32(0, base + SATAPHYADDR_REG);
}

static void sata_rcar_gen1_phy_init(struct sata_rcar_priv *priv)
{
	sata_rcar_gen1_phy_preinit(priv);
	sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0);
	sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1);
	sata_rcar_gen1_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0);
	sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0);
	sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1);
	sata_rcar_gen1_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0);
}

static void sata_rcar_gen2_phy_init(struct sata_rcar_priv *priv)
{
	void __iomem *base = priv->base;

	iowrite32(RCAR_GEN2_PHY_CTL1, base + RCAR_GEN2_PHY_CTL1_REG);
	iowrite32(RCAR_GEN2_PHY_CTL2, base + RCAR_GEN2_PHY_CTL2_REG);
	iowrite32(RCAR_GEN2_PHY_CTL3, base + RCAR_GEN2_PHY_CTL3_REG);
	iowrite32(RCAR_GEN2_PHY_CTL4, base + RCAR_GEN2_PHY_CTL4_REG);
	iowrite32(RCAR_GEN2_PHY_CTL5 | RCAR_GEN2_PHY_CTL5_DC |
		  RCAR_GEN2_PHY_CTL5_TR, base + RCAR_GEN2_PHY_CTL5_REG);
}

static void sata_rcar_freeze(struct ata_port *ap)
{
	struct sata_rcar_priv *priv = ap->host->private_data;

	/* mask */
	iowrite32(priv->sataint_mask, priv->base + SATAINTMASK_REG);

	ata_sff_freeze(ap);
}

static void sata_rcar_thaw(struct ata_port *ap)
{
	struct sata_rcar_priv *priv = ap->host->private_data;
	void __iomem *base = priv->base;

	/* ack */
	iowrite32(~(u32)SATA_RCAR_INT_MASK, base + SATAINTSTAT_REG);

	ata_sff_thaw(ap);

Annotation

Implementation Notes