drivers/bus/qcom-ssc-block-bus.c

Source file repositories/reference/linux-study-clean/drivers/bus/qcom-ssc-block-bus.c

File Facts

System
Linux kernel
Corpus path
drivers/bus/qcom-ssc-block-bus.c
Extension
.c
Size
10642 bytes
Lines
391
Domain
Driver Families
Bucket
drivers/bus
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct qcom_ssc_block_bus_data {
	const char *const *pd_names;
	struct device *pds[ARRAY_SIZE(qcom_ssc_block_pd_names)];
	char __iomem *reg_mpm_sscaon_config0;
	char __iomem *reg_mpm_sscaon_config1;
	struct regmap *halt_map;
	struct clk *xo_clk;
	struct clk *aggre2_clk;
	struct clk *gcc_im_sleep_clk;
	struct clk *aggre2_north_clk;
	struct clk *ssc_xo_clk;
	struct clk *ssc_ahbs_clk;
	struct reset_control *ssc_bcr;
	struct reset_control *ssc_reset;
	u32 ssc_axi_halt;
	int num_pds;
};

static void reg32_set_bits(char __iomem *reg, u32 value)
{
	u32 tmp = ioread32(reg);

	iowrite32(tmp | value, reg);
}

static void reg32_clear_bits(char __iomem *reg, u32 value)
{
	u32 tmp = ioread32(reg);

	iowrite32(tmp & (~value), reg);
}

static int qcom_ssc_block_bus_init(struct device *dev)
{
	int ret;

	struct qcom_ssc_block_bus_data *data = dev_get_drvdata(dev);

	ret = clk_prepare_enable(data->xo_clk);
	if (ret) {
		dev_err(dev, "error enabling xo_clk: %d\n", ret);
		goto err_xo_clk;
	}

	ret = clk_prepare_enable(data->aggre2_clk);
	if (ret) {
		dev_err(dev, "error enabling aggre2_clk: %d\n", ret);
		goto err_aggre2_clk;
	}

	ret = clk_prepare_enable(data->gcc_im_sleep_clk);
	if (ret) {
		dev_err(dev, "error enabling gcc_im_sleep_clk: %d\n", ret);
		goto err_gcc_im_sleep_clk;
	}

	/*
	 * We need to intervene here because the HW logic driving these signals cannot handle
	 * initialization after power collapse by itself.
	 */
	reg32_clear_bits(data->reg_mpm_sscaon_config0,
			 SSCAON_CONFIG0_CLAMP_EN_OVRD | SSCAON_CONFIG0_CLAMP_EN_OVRD_VAL);
	/* override few_ack/rest_ack */
	reg32_clear_bits(data->reg_mpm_sscaon_config1, BIT(31));

	ret = clk_prepare_enable(data->aggre2_north_clk);
	if (ret) {
		dev_err(dev, "error enabling aggre2_north_clk: %d\n", ret);
		goto err_aggre2_north_clk;
	}

	ret = reset_control_deassert(data->ssc_reset);
	if (ret) {
		dev_err(dev, "error deasserting ssc_reset: %d\n", ret);
		goto err_ssc_reset;
	}

	ret = reset_control_deassert(data->ssc_bcr);
	if (ret) {
		dev_err(dev, "error deasserting ssc_bcr: %d\n", ret);
		goto err_ssc_bcr;
	}

	regmap_write(data->halt_map, data->ssc_axi_halt + AXI_HALTREQ_REG, 0);

	ret = clk_prepare_enable(data->ssc_xo_clk);
	if (ret) {
		dev_err(dev, "error deasserting ssc_xo_clk: %d\n", ret);
		goto err_ssc_xo_clk;
	}

Annotation

Implementation Notes