drivers/clk/at91/clk-plldiv.c
Source file repositories/reference/linux-study-clean/drivers/clk/at91/clk-plldiv.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/clk/at91/clk-plldiv.c- Extension
.c- Size
- 2376 bytes
- Lines
- 116
- Domain
- Driver Families
- Bucket
- drivers/clk
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/clk-provider.hlinux/clkdev.hlinux/clk/at91_pmc.hlinux/of.hlinux/mfd/syscon.hlinux/regmap.hpmc.h
Detected Declarations
struct clk_plldivfunction clk_plldiv_recalc_ratefunction clk_plldiv_determine_ratefunction clk_plldiv_set_ratefunction at91_clk_register_plldiv
Annotated Snippet
struct clk_plldiv {
struct clk_hw hw;
struct regmap *regmap;
};
static unsigned long clk_plldiv_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_plldiv *plldiv = to_clk_plldiv(hw);
unsigned int mckr;
regmap_read(plldiv->regmap, AT91_PMC_MCKR, &mckr);
if (mckr & AT91_PMC_PLLADIV2)
return parent_rate / 2;
return parent_rate;
}
static int clk_plldiv_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
unsigned long div;
if (req->rate > req->best_parent_rate) {
req->rate = req->best_parent_rate;
return 0;
}
div = req->best_parent_rate / 2;
if (req->rate < div) {
req->rate = div;
return 0;
}
if (req->rate - div < req->best_parent_rate - req->rate) {
req->rate = div;
return 0;
}
req->rate = req->best_parent_rate;
return 0;
}
static int clk_plldiv_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_plldiv *plldiv = to_clk_plldiv(hw);
if ((parent_rate != rate) && (parent_rate / 2 != rate))
return -EINVAL;
regmap_update_bits(plldiv->regmap, AT91_PMC_MCKR, AT91_PMC_PLLADIV2,
parent_rate != rate ? AT91_PMC_PLLADIV2 : 0);
return 0;
}
static const struct clk_ops plldiv_ops = {
.recalc_rate = clk_plldiv_recalc_rate,
.determine_rate = clk_plldiv_determine_rate,
.set_rate = clk_plldiv_set_rate,
};
struct clk_hw * __init
at91_clk_register_plldiv(struct regmap *regmap, const char *name,
const char *parent_name)
{
struct clk_plldiv *plldiv;
struct clk_hw *hw;
struct clk_init_data init;
int ret;
plldiv = kzalloc_obj(*plldiv);
if (!plldiv)
return ERR_PTR(-ENOMEM);
init.name = name;
init.ops = &plldiv_ops;
init.parent_names = parent_name ? &parent_name : NULL;
init.num_parents = parent_name ? 1 : 0;
init.flags = CLK_SET_RATE_GATE;
plldiv->hw.init = &init;
plldiv->regmap = regmap;
Annotation
- Immediate include surface: `linux/clk-provider.h`, `linux/clkdev.h`, `linux/clk/at91_pmc.h`, `linux/of.h`, `linux/mfd/syscon.h`, `linux/regmap.h`, `pmc.h`.
- Detected declarations: `struct clk_plldiv`, `function clk_plldiv_recalc_rate`, `function clk_plldiv_determine_rate`, `function clk_plldiv_set_rate`, `function at91_clk_register_plldiv`.
- Atlas domain: Driver Families / drivers/clk.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.