drivers/clk/at91/clk-sam9x60-pll.c
Source file repositories/reference/linux-study-clean/drivers/clk/at91/clk-sam9x60-pll.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/clk/at91/clk-sam9x60-pll.c- Extension
.c- Size
- 21850 bytes
- Lines
- 797
- Domain
- Driver Families
- Bucket
- drivers/clk
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bitfield.hlinux/clk.hlinux/clk-provider.hlinux/clkdev.hlinux/clk/at91_pmc.hlinux/of.hlinux/mfd/syscon.hlinux/regmap.hpmc.h
Detected Declarations
struct sam9x60_pll_corestruct sam9x60_fracstruct sam9x60_divfunction sam9x60_pll_readyfunction sam9x60_frac_pll_readyfunction sam9x60_frac_pll_recalc_ratefunction sam9x60_frac_pll_setfunction sam9x60_frac_pll_preparefunction sam9x60_frac_pll_unpreparefunction sam9x60_frac_pll_is_preparedfunction sam9x60_frac_pll_compute_mul_fracfunction sam9x60_frac_pll_determine_ratefunction sam9x60_frac_pll_set_ratefunction sam9x60_frac_pll_set_rate_chgfunction sam9x60_frac_pll_save_contextfunction sam9x60_frac_pll_restore_contextfunction sam9x60_div_pll_set_divfunction sam9x60_div_pll_setfunction sam9x60_div_pll_preparefunction sam9x60_div_pll_unpreparefunction sam9x60_div_pll_is_preparedfunction sam9x60_div_pll_recalc_ratefunction sam9x60_fixed_div_pll_recalc_ratefunction sam9x60_div_pll_compute_divfunction sam9x60_div_pll_determine_ratefunction sam9x60_div_pll_set_ratefunction sam9x60_div_pll_set_rate_chgfunction sam9x60_div_pll_save_contextfunction sam9x60_div_pll_restore_contextfunction sam9x60_div_pll_notifier_fnfunction sam9x60_clk_register_frac_pllfunction sam9x60_clk_register_div_pll
Annotated Snippet
struct sam9x60_pll_core {
struct regmap *regmap;
spinlock_t *lock;
const struct clk_pll_characteristics *characteristics;
const struct clk_pll_layout *layout;
struct clk_hw hw;
u8 id;
};
struct sam9x60_frac {
struct sam9x60_pll_core core;
struct at91_clk_pms pms;
u32 frac;
u16 mul;
};
struct sam9x60_div {
struct sam9x60_pll_core core;
struct at91_clk_pms pms;
u8 div;
u8 safe_div;
};
#define to_sam9x60_pll_core(hw) container_of(hw, struct sam9x60_pll_core, hw)
#define to_sam9x60_frac(core) container_of(core, struct sam9x60_frac, core)
#define to_sam9x60_div(core) container_of(core, struct sam9x60_div, core)
static struct sam9x60_div *notifier_div;
static inline bool sam9x60_pll_ready(struct regmap *regmap, int id)
{
unsigned int status;
regmap_read(regmap, AT91_PMC_PLL_ISR0, &status);
return !!(status & BIT(id));
}
static bool sam9x60_frac_pll_ready(struct regmap *regmap, u8 id)
{
return sam9x60_pll_ready(regmap, id);
}
static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
struct sam9x60_frac *frac = to_sam9x60_frac(core);
unsigned long freq;
freq = parent_rate * (frac->mul + 1) +
DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22));
if (core->layout->div2)
freq >>= 1;
return freq;
}
static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
{
struct sam9x60_frac *frac = to_sam9x60_frac(core);
struct regmap *regmap = core->regmap;
unsigned int val, cfrac, cmul;
unsigned long flags;
spin_lock_irqsave(core->lock, flags);
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;
if (sam9x60_frac_pll_ready(regmap, core->id) &&
(cmul == frac->mul && cfrac == frac->frac))
goto unlock;
/* Load recommended value for PMC_PLL_ACR */
val = core->characteristics->acr;
regmap_write(regmap, AT91_PMC_PLL_ACR, val);
regmap_write(regmap, AT91_PMC_PLL_CTRL1,
(frac->mul << core->layout->mul_shift) |
(frac->frac << core->layout->frac_shift));
if (core->characteristics->upll) {
/* Enable the UTMI internal bandgap */
val |= AT91_PMC_PLL_ACR_UTMIBG;
regmap_write(regmap, AT91_PMC_PLL_ACR, val);
Annotation
- Immediate include surface: `linux/bitfield.h`, `linux/clk.h`, `linux/clk-provider.h`, `linux/clkdev.h`, `linux/clk/at91_pmc.h`, `linux/of.h`, `linux/mfd/syscon.h`, `linux/regmap.h`.
- Detected declarations: `struct sam9x60_pll_core`, `struct sam9x60_frac`, `struct sam9x60_div`, `function sam9x60_pll_ready`, `function sam9x60_frac_pll_ready`, `function sam9x60_frac_pll_recalc_rate`, `function sam9x60_frac_pll_set`, `function sam9x60_frac_pll_prepare`, `function sam9x60_frac_pll_unprepare`, `function sam9x60_frac_pll_is_prepared`.
- Atlas domain: Driver Families / drivers/clk.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.