drivers/clk/at91/sama5d3.c

Source file repositories/reference/linux-study-clean/drivers/clk/at91/sama5d3.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/at91/sama5d3.c
Extension
.c
Size
7901 bytes
Lines
270
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
#include <linux/clk-provider.h>
#include <linux/mfd/syscon.h>
#include <linux/slab.h>

#include <dt-bindings/clock/at91.h>

#include "pmc.h"

static DEFINE_SPINLOCK(mck_lock);

static const struct clk_master_characteristics mck_characteristics = {
	.output = { .min = 0, .max = 166000000 },
	.divisors = { 1, 2, 4, 3 },
};

static u8 plla_out[] = { 0 };

static u16 plla_icpll[] = { 0 };

static const struct clk_range plla_outputs[] = {
	{ .min = 400000000, .max = 1000000000 },
};

static const struct clk_pll_characteristics plla_characteristics = {
	.input = { .min = 8000000, .max = 50000000 },
	.num_output = ARRAY_SIZE(plla_outputs),
	.output = plla_outputs,
	.icpll = plla_icpll,
	.out = plla_out,
};

static const struct clk_pcr_layout sama5d3_pcr_layout = {
	.offset = 0x10c,
	.cmd = BIT(12),
	.pid_mask = GENMASK(6, 0),
	.div_mask = GENMASK(17, 16),
};

static const struct {
	char *n;
	char *p;
	unsigned long flags;
	u8 id;
} sama5d3_systemck[] = {
	/*
	 * ddrck feeds DDR controller and is enabled by bootloader thus we need
	 * to keep it enabled in case there is no Linux consumer for it.
	 */
	{ .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL },
	{ .n = "lcdck", .p = "masterck_div", .id = 3 },
	{ .n = "smdck", .p = "smdclk",       .id = 4 },
	{ .n = "uhpck", .p = "usbck",        .id = 6 },
	{ .n = "udpck", .p = "usbck",        .id = 7 },
	{ .n = "pck0",  .p = "prog0",        .id = 8 },
	{ .n = "pck1",  .p = "prog1",        .id = 9 },
	{ .n = "pck2",  .p = "prog2",        .id = 10 },
};

static const struct {
	char *n;
	u8 id;
	struct clk_range r;
	unsigned long flags;
} sama5d3_periphck[] = {
	{ .n = "dbgu_clk", .id = 2, },
	{ .n = "hsmc_clk", .id = 5, },
	{ .n = "pioA_clk", .id = 6, },
	{ .n = "pioB_clk", .id = 7, },
	{ .n = "pioC_clk", .id = 8, },
	{ .n = "pioD_clk", .id = 9, },
	{ .n = "pioE_clk", .id = 10, },
	{ .n = "usart0_clk", .id = 12, .r = { .min = 0, .max = 83000000 }, },
	{ .n = "usart1_clk", .id = 13, .r = { .min = 0, .max = 83000000 }, },
	{ .n = "usart2_clk", .id = 14, .r = { .min = 0, .max = 83000000 }, },
	{ .n = "usart3_clk", .id = 15, .r = { .min = 0, .max = 83000000 }, },
	{ .n = "uart0_clk", .id = 16, .r = { .min = 0, .max = 83000000 }, },
	{ .n = "uart1_clk", .id = 17, .r = { .min = 0, .max = 83000000 }, },
	{ .n = "twi0_clk", .id = 18, .r = { .min = 0, .max = 41500000 }, },
	{ .n = "twi1_clk", .id = 19, .r = { .min = 0, .max = 41500000 }, },
	{ .n = "twi2_clk", .id = 20, .r = { .min = 0, .max = 41500000 }, },
	{ .n = "mci0_clk", .id = 21, },
	{ .n = "mci1_clk", .id = 22, },
	{ .n = "mci2_clk", .id = 23, },
	{ .n = "spi0_clk", .id = 24, .r = { .min = 0, .max = 166000000 }, },
	{ .n = "spi1_clk", .id = 25, .r = { .min = 0, .max = 166000000 }, },
	{ .n = "tcb0_clk", .id = 26, .r = { .min = 0, .max = 166000000 }, },
	{ .n = "tcb1_clk", .id = 27, .r = { .min = 0, .max = 166000000 }, },
	{ .n = "pwm_clk", .id = 28, },
	{ .n = "adc_clk", .id = 29, .r = { .min = 0, .max = 83000000 }, },

Annotation

Implementation Notes