drivers/clk/axs10x/pll_clock.c

Source file repositories/reference/linux-study-clean/drivers/clk/axs10x/pll_clock.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/axs10x/pll_clock.c
Extension
.c
Size
8519 bytes
Lines
336
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct axs10x_pll_cfg {
	u32 rate;
	u32 idiv;
	u32 fbdiv;
	u32 odiv;
};

static const struct axs10x_pll_cfg arc_pll_cfg[] = {
	{ 33333333,  1, 1,  1 },
	{ 50000000,  1, 30, 20 },
	{ 75000000,  2, 45, 10 },
	{ 90000000,  2, 54, 10 },
	{ 100000000, 1, 30, 10 },
	{ 125000000, 2, 45, 6 },
	{}
};

static const struct axs10x_pll_cfg pgu_pll_cfg[] = {
	{ 25200000, 1, 84, 90 },
	{ 50000000, 1, 100, 54 },
	{ 74250000, 1, 44, 16 },
	{}
};

struct axs10x_pll_clk {
	struct clk_hw hw;
	void __iomem *base;
	void __iomem *lock;
	const struct axs10x_pll_cfg *pll_cfg;
	struct device *dev;
};

static inline void axs10x_pll_write(struct axs10x_pll_clk *clk, u32 reg,
				    u32 val)
{
	iowrite32(val, clk->base + reg);
}

static inline u32 axs10x_pll_read(struct axs10x_pll_clk *clk, u32 reg)
{
	return ioread32(clk->base + reg);
}

static inline struct axs10x_pll_clk *to_axs10x_pll_clk(struct clk_hw *hw)
{
	return container_of(hw, struct axs10x_pll_clk, hw);
}

static inline u32 axs10x_div_get_value(u32 reg)
{
	if (PLL_REG_GET_BYPASS(reg))
		return 1;

	return PLL_REG_GET_HIGH(reg) + PLL_REG_GET_LOW(reg);
}

static inline u32 axs10x_encode_div(unsigned int id, int upd)
{
	u32 div = 0;

	PLL_REG_SET_LOW(div, (id % 2 == 0) ? id >> 1 : (id >> 1) + 1);
	PLL_REG_SET_HIGH(div, id >> 1);
	PLL_REG_SET_EDGE(div, id % 2);
	PLL_REG_SET_BYPASS(div, id == 1 ? 1 : 0);
	PLL_REG_SET_NOUPD(div, upd == 0 ? 1 : 0);

	return div;
}

static unsigned long axs10x_pll_recalc_rate(struct clk_hw *hw,
					    unsigned long parent_rate)
{
	u64 rate;
	u32 idiv, fbdiv, odiv;
	struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);

	idiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_IDIV));
	fbdiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_FBDIV));
	odiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_ODIV));

	rate = (u64)parent_rate * fbdiv;
	do_div(rate, idiv * odiv);

	return rate;
}

static int axs10x_pll_determine_rate(struct clk_hw *hw,
				     struct clk_rate_request *req)
{
	int i;

Annotation

Implementation Notes