drivers/clk/bcm/clk-cygnus.c

Source file repositories/reference/linux-study-clean/drivers/clk/bcm/clk-cygnus.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/bcm/clk-cygnus.c
Extension
.c
Size
9704 bytes
Lines
305
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
// Copyright (C) 2014 Broadcom Corporation

#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/clkdev.h>
#include <linux/of_address.h>
#include <linux/delay.h>

#include <dt-bindings/clock/bcm-cygnus.h>
#include "clk-iproc.h"

#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }

#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
	.pwr_shift = ps, .iso_shift = is }

#define SW_CTRL_VAL(o, s) { .offset = o, .shift = s, }

#define ASIU_DIV_VAL(o, es, hs, hw, ls, lw) \
		{ .offset = o, .en_shift = es, .high_shift = hs, \
		.high_width = hw, .low_shift = ls, .low_width = lw }

#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \
	.p_reset_shift = prs }

#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\
	.ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas,    \
	.ka_width = kaw }

#define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }

#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
	.hold_shift = hs, .bypass_shift = bs }

#define ASIU_GATE_VAL(o, es) { .offset = o, .en_shift = es }

static void __init cygnus_armpll_init(struct device_node *node)
{
	iproc_armpll_setup(node);
}
CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);

static const struct iproc_pll_ctrl genpll = {
	.flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
		IPROC_CLK_PLL_NEEDS_SW_CFG,
	.aon = AON_VAL(0x0, 2, 1, 0),
	.reset = RESET_VAL(0x0, 11, 10),
	.dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
	.sw_ctrl = SW_CTRL_VAL(0x10, 31),
	.ndiv_int = REG_VAL(0x10, 20, 10),
	.ndiv_frac = REG_VAL(0x10, 0, 20),
	.pdiv = REG_VAL(0x14, 0, 4),
	.vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c),
	.status = REG_VAL(0x28, 12, 1),
};

static const struct iproc_clk_ctrl genpll_clk[] = {
	[BCM_CYGNUS_GENPLL_AXI21_CLK] = {
		.channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
		.flags = IPROC_CLK_AON,
		.enable = ENABLE_VAL(0x4, 6, 0, 12),
		.mdiv = REG_VAL(0x20, 0, 8),
	},
	[BCM_CYGNUS_GENPLL_250MHZ_CLK] = {
		.channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
		.flags = IPROC_CLK_AON,
		.enable = ENABLE_VAL(0x4, 7, 1, 13),
		.mdiv = REG_VAL(0x20, 10, 8),
	},
	[BCM_CYGNUS_GENPLL_IHOST_SYS_CLK] = {
		.channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
		.flags = IPROC_CLK_AON,
		.enable = ENABLE_VAL(0x4, 8, 2, 14),
		.mdiv = REG_VAL(0x20, 20, 8),
	},
	[BCM_CYGNUS_GENPLL_ENET_SW_CLK] = {
		.channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK,
		.flags = IPROC_CLK_AON,
		.enable = ENABLE_VAL(0x4, 9, 3, 15),
		.mdiv = REG_VAL(0x24, 0, 8),
	},
	[BCM_CYGNUS_GENPLL_AUDIO_125_CLK] = {
		.channel = BCM_CYGNUS_GENPLL_AUDIO_125_CLK,
		.flags = IPROC_CLK_AON,
		.enable = ENABLE_VAL(0x4, 10, 4, 16),
		.mdiv = REG_VAL(0x24, 10, 8),

Annotation

Implementation Notes