drivers/clk/bcm/clk-ns2.c
Source file repositories/reference/linux-study-clean/drivers/clk/bcm/clk-ns2.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/clk/bcm/clk-ns2.c- Extension
.c- Size
- 8605 bytes
- Lines
- 279
- Domain
- Driver Families
- Bucket
- drivers/clk
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/err.hlinux/clk-provider.hlinux/io.hlinux/of.hlinux/of_address.hdt-bindings/clock/bcm-ns2.hclk-iproc.h
Detected Declarations
function ns2_genpll_scr_clk_initfunction ns2_genpll_sw_clk_initfunction ns2_lcpll_ddr_clk_initfunction ns2_lcpll_ports_clk_init
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (C) 2015 Broadcom Corporation
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <dt-bindings/clock/bcm-ns2.h>
#include "clk-iproc.h"
#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
.pwr_shift = ps, .iso_shift = is }
#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \
.p_reset_shift = prs }
#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\
.ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
.ka_width = kaw }
#define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }
#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
.hold_shift = hs, .bypass_shift = bs }
static const struct iproc_pll_ctrl genpll_scr = {
.flags = IPROC_CLK_AON | IPROC_CLK_PLL_SPLIT_STAT_CTRL,
.aon = AON_VAL(0x0, 1, 15, 12),
.reset = RESET_VAL(0x4, 2, 1),
.dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 2, 3),
.ndiv_int = REG_VAL(0x8, 4, 10),
.pdiv = REG_VAL(0x8, 0, 4),
.vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
.status = REG_VAL(0x0, 27, 1),
};
static const struct iproc_clk_ctrl genpll_scr_clk[] = {
/* bypass_shift, the last value passed into ENABLE_VAL(), is not defined
* in NS2. However, it doesn't appear to be used anywhere, so setting
* it to 0.
*/
[BCM_NS2_GENPLL_SCR_SCR_CLK] = {
.channel = BCM_NS2_GENPLL_SCR_SCR_CLK,
.flags = IPROC_CLK_AON,
.enable = ENABLE_VAL(0x0, 18, 12, 0),
.mdiv = REG_VAL(0x18, 0, 8),
},
[BCM_NS2_GENPLL_SCR_FS_CLK] = {
.channel = BCM_NS2_GENPLL_SCR_FS_CLK,
.flags = IPROC_CLK_AON,
.enable = ENABLE_VAL(0x0, 19, 13, 0),
.mdiv = REG_VAL(0x18, 8, 8),
},
[BCM_NS2_GENPLL_SCR_AUDIO_CLK] = {
.channel = BCM_NS2_GENPLL_SCR_AUDIO_CLK,
.flags = IPROC_CLK_AON,
.enable = ENABLE_VAL(0x0, 20, 14, 0),
.mdiv = REG_VAL(0x14, 0, 8),
},
[BCM_NS2_GENPLL_SCR_CH3_UNUSED] = {
.channel = BCM_NS2_GENPLL_SCR_CH3_UNUSED,
.flags = IPROC_CLK_AON,
.enable = ENABLE_VAL(0x0, 21, 15, 0),
.mdiv = REG_VAL(0x14, 8, 8),
},
[BCM_NS2_GENPLL_SCR_CH4_UNUSED] = {
.channel = BCM_NS2_GENPLL_SCR_CH4_UNUSED,
.flags = IPROC_CLK_AON,
.enable = ENABLE_VAL(0x0, 22, 16, 0),
.mdiv = REG_VAL(0x14, 16, 8),
},
[BCM_NS2_GENPLL_SCR_CH5_UNUSED] = {
.channel = BCM_NS2_GENPLL_SCR_CH5_UNUSED,
.flags = IPROC_CLK_AON,
.enable = ENABLE_VAL(0x0, 23, 17, 0),
.mdiv = REG_VAL(0x14, 24, 8),
},
};
static void __init ns2_genpll_scr_clk_init(struct device_node *node)
{
iproc_pll_clk_setup(node, &genpll_scr, NULL, 0, genpll_scr_clk,
ARRAY_SIZE(genpll_scr_clk));
}
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/err.h`, `linux/clk-provider.h`, `linux/io.h`, `linux/of.h`, `linux/of_address.h`, `dt-bindings/clock/bcm-ns2.h`, `clk-iproc.h`.
- Detected declarations: `function ns2_genpll_scr_clk_init`, `function ns2_genpll_sw_clk_init`, `function ns2_lcpll_ddr_clk_init`, `function ns2_lcpll_ports_clk_init`.
- Atlas domain: Driver Families / drivers/clk.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.