drivers/clk/berlin/bg2.c

Source file repositories/reference/linux-study-clean/drivers/clk/berlin/bg2.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/berlin/bg2.c
Extension
.c
Size
19069 bytes
Lines
688
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2014 Marvell Technology Group Ltd.
 *
 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>

#include <dt-bindings/clock/berlin2.h>

#include "berlin2-avpll.h"
#include "berlin2-div.h"
#include "berlin2-pll.h"
#include "common.h"

#define REG_PINMUX0		0x0000
#define REG_PINMUX1		0x0004
#define REG_SYSPLLCTL0		0x0014
#define REG_SYSPLLCTL4		0x0024
#define REG_MEMPLLCTL0		0x0028
#define REG_MEMPLLCTL4		0x0038
#define REG_CPUPLLCTL0		0x003c
#define REG_CPUPLLCTL4		0x004c
#define REG_AVPLLCTL0		0x0050
#define REG_AVPLLCTL31		0x00cc
#define REG_AVPLLCTL62		0x0148
#define REG_PLLSTATUS		0x014c
#define REG_CLKENABLE		0x0150
#define REG_CLKSELECT0		0x0154
#define REG_CLKSELECT1		0x0158
#define REG_CLKSELECT2		0x015c
#define REG_CLKSELECT3		0x0160
#define REG_CLKSWITCH0		0x0164
#define REG_CLKSWITCH1		0x0168
#define REG_RESET_TRIGGER	0x0178
#define REG_RESET_STATUS0	0x017c
#define REG_RESET_STATUS1	0x0180
#define REG_SW_GENERIC0		0x0184
#define REG_SW_GENERIC3		0x0190
#define REG_PRODUCTID		0x01cc
#define REG_PRODUCTID_EXT	0x01d0
#define REG_GFX3DCORE_CLKCTL	0x022c
#define REG_GFX3DSYS_CLKCTL	0x0230
#define REG_ARC_CLKCTL		0x0234
#define REG_VIP_CLKCTL		0x0238
#define REG_SDIO0XIN_CLKCTL	0x023c
#define REG_SDIO1XIN_CLKCTL	0x0240
#define REG_GFX3DEXTRA_CLKCTL	0x0244
#define REG_GFX3D_RESET		0x0248
#define REG_GC360_CLKCTL	0x024c
#define REG_SDIO_DLLMST_CLKCTL	0x0250

/*
 * BG2/BG2CD SoCs have the following audio/video I/O units:
 *
 * audiohd: HDMI TX audio
 * audio0:  7.1ch TX
 * audio1:  2ch TX
 * audio2:  2ch RX
 * audio3:  SPDIF TX
 * video0:  HDMI video
 * video1:  Secondary video
 * video2:  SD auxiliary video
 *
 * There are no external audio clocks (ACLKI0, ACLKI1) and
 * only one external video clock (VCLKI0).
 *
 * Currently missing bits and pieces:
 * - audio_fast_pll is unknown
 * - audiohd_pll is unknown
 * - video0_pll is unknown
 * - audio[023], audiohd parent pll is assumed to be audio_fast_pll
 *
 */

#define	MAX_CLKS 41
static struct clk_hw_onecell_data *clk_data;
static DEFINE_SPINLOCK(lock);
static void __iomem *gbase;

enum {
	REFCLK, VIDEO_EXT0,

Annotation

Implementation Notes