drivers/clk/clk-asm9260.c

Source file repositories/reference/linux-study-clean/drivers/clk/clk-asm9260.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/clk-asm9260.c
Extension
.c
Size
11131 bytes
Lines
337
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct asm9260_div_clk {
	unsigned int idx;
	const char *name;
	const char *parent_name;
	u32 reg;
};

struct asm9260_gate_data {
	unsigned int idx;
	const char *name;
	const char *parent_name;
	u32 reg;
	u8 bit_idx;
	unsigned long flags;
};

struct asm9260_mux_clock {
	u8			mask;
	u32			*table;
	const char		*name;
	const struct clk_parent_data *parent_data;
	u8			num_parents;
	unsigned long		offset;
	unsigned long		flags;
};

static void __iomem *base;

static const struct asm9260_div_clk asm9260_div_clks[] __initconst = {
	{ CLKID_SYS_CPU,	"cpu_div", "main_gate", HW_CPUCLKDIV },
	{ CLKID_SYS_AHB,	"ahb_div", "cpu_div", HW_SYSAHBCLKDIV },

	/* i2s has two dividers: one for only external mclk and internal
	 * divider for all clks. */
	{ CLKID_SYS_I2S0M,	"i2s0m_div", "i2s0_mclk",  HW_I2S0MCLKDIV },
	{ CLKID_SYS_I2S1M,	"i2s1m_div", "i2s1_mclk",  HW_I2S1MCLKDIV },
	{ CLKID_SYS_I2S0S,	"i2s0s_div", "i2s0_gate",  HW_I2S0SCLKDIV },
	{ CLKID_SYS_I2S1S,	"i2s1s_div", "i2s0_gate",  HW_I2S1SCLKDIV },

	{ CLKID_SYS_UART0,	"uart0_div", "uart_gate", HW_UART0CLKDIV },
	{ CLKID_SYS_UART1,	"uart1_div", "uart_gate", HW_UART1CLKDIV },
	{ CLKID_SYS_UART2,	"uart2_div", "uart_gate", HW_UART2CLKDIV },
	{ CLKID_SYS_UART3,	"uart3_div", "uart_gate", HW_UART3CLKDIV },
	{ CLKID_SYS_UART4,	"uart4_div", "uart_gate", HW_UART4CLKDIV },
	{ CLKID_SYS_UART5,	"uart5_div", "uart_gate", HW_UART5CLKDIV },
	{ CLKID_SYS_UART6,	"uart6_div", "uart_gate", HW_UART6CLKDIV },
	{ CLKID_SYS_UART7,	"uart7_div", "uart_gate", HW_UART7CLKDIV },
	{ CLKID_SYS_UART8,	"uart8_div", "uart_gate", HW_UART8CLKDIV },
	{ CLKID_SYS_UART9,	"uart9_div", "uart_gate", HW_UART9CLKDIV },

	{ CLKID_SYS_SPI0,	"spi0_div",	"main_gate", HW_SPI0CLKDIV },
	{ CLKID_SYS_SPI1,	"spi1_div",	"main_gate", HW_SPI1CLKDIV },
	{ CLKID_SYS_QUADSPI,	"quadspi_div",	"main_gate", HW_QUADSPICLKDIV },
	{ CLKID_SYS_SSP0,	"ssp0_div",	"main_gate", HW_SSP0CLKDIV },
	{ CLKID_SYS_NAND,	"nand_div",	"main_gate", HW_NANDCLKDIV },
	{ CLKID_SYS_TRACE,	"trace_div",	"main_gate", HW_TRACECLKDIV },
	{ CLKID_SYS_CAMM,	"camm_div",	"main_gate", HW_CAMMCLKDIV },
	{ CLKID_SYS_MAC,	"mac_div",	"main_gate", HW_MACCLKDIV },
	{ CLKID_SYS_LCD,	"lcd_div",	"main_gate", HW_LCDCLKDIV },
	{ CLKID_SYS_ADCANA,	"adcana_div",	"main_gate", HW_ADCANACLKDIV },

	{ CLKID_SYS_WDT,	"wdt_div",	"wdt_gate",    HW_WDTCLKDIV },
	{ CLKID_SYS_CLKOUT,	"clkout_div",	"clkout_gate", HW_CLKOUTCLKDIV },
};

static const struct asm9260_gate_data asm9260_mux_gates[] __initconst = {
	{ 0, "main_gate",	"main_mux",	HW_MAINCLKUEN,	0 },
	{ 0, "uart_gate",	"uart_mux",	HW_UARTCLKUEN,	0 },
	{ 0, "i2s0_gate",	"i2s0_mux",	HW_I2S0CLKUEN,	0 },
	{ 0, "i2s1_gate",	"i2s1_mux",	HW_I2S1CLKUEN,	0 },
	{ 0, "wdt_gate",	"wdt_mux",	HW_WDTCLKUEN,	0 },
	{ 0, "clkout_gate",	"clkout_mux",	HW_CLKOUTCLKUEN, 0 },
};
static const struct asm9260_gate_data asm9260_ahb_gates[] __initconst = {
	/* ahb gates */
	{ CLKID_AHB_ROM,	"rom",		"ahb_div",
		HW_AHBCLKCTRL0,	1, CLK_IGNORE_UNUSED},
	{ CLKID_AHB_RAM,	"ram",		"ahb_div",
		HW_AHBCLKCTRL0,	2, CLK_IGNORE_UNUSED},
	{ CLKID_AHB_GPIO,	"gpio",		"ahb_div",
		HW_AHBCLKCTRL0,	4 },
	{ CLKID_AHB_MAC,	"mac",		"ahb_div",
		HW_AHBCLKCTRL0,	5 },
	{ CLKID_AHB_EMI,	"emi",		"ahb_div",
		HW_AHBCLKCTRL0,	6, CLK_IGNORE_UNUSED},
	{ CLKID_AHB_USB0,	"usb0",		"ahb_div",
		HW_AHBCLKCTRL0,	7 },
	{ CLKID_AHB_USB1,	"usb1",		"ahb_div",
		HW_AHBCLKCTRL0,	8 },
	{ CLKID_AHB_DMA0,	"dma0",		"ahb_div",

Annotation

Implementation Notes