drivers/clk/clk-fsl-sai.c

Source file repositories/reference/linux-study-clean/drivers/clk/clk-fsl-sai.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/clk-fsl-sai.c
Extension
.c
Size
4324 bytes
Lines
178
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct fsl_sai_data {
	unsigned int	offset;	/* Register offset */
	bool		have_mclk; /* Have MCLK control */
};

struct fsl_sai_clk {
	const struct fsl_sai_data *data;
	struct clk_divider bclk_div;
	struct clk_divider mclk_div;
	struct clk_gate bclk_gate;
	struct clk_gate mclk_gate;
	struct clk_hw *bclk_hw;
	struct clk_hw *mclk_hw;
	spinlock_t lock;
};

static struct clk_hw *
fsl_sai_of_clk_get(struct of_phandle_args *clkspec, void *data)
{
	struct fsl_sai_clk *sai_clk = data;

	if (clkspec->args_count == 0)
		return sai_clk->bclk_hw;

	if (clkspec->args_count == 1) {
		if (clkspec->args[0] == 0)
			return sai_clk->bclk_hw;
		if (sai_clk->data->have_mclk && clkspec->args[0] == 1)
			return sai_clk->mclk_hw;
	}

	return ERR_PTR(-EINVAL);
}

static int fsl_sai_clk_register(struct device *dev, void __iomem *base,
				spinlock_t *lock, struct clk_divider *div,
				struct clk_gate *gate, struct clk_hw **hw,
				const int gate_bit, const int dir_bit,
				const int div_reg, char *name)
{
	const struct fsl_sai_data *data = device_get_match_data(dev);
	struct clk_parent_data pdata = { .index = 0 };
	struct clk_hw *chw;
	char *cname;

	gate->reg = base + data->offset + I2S_CSR;
	gate->bit_idx = gate_bit;
	gate->lock = lock;

	div->reg = base + div_reg;
	div->shift = CR2_DIV_SHIFT;
	div->width = CR2_DIV_WIDTH;
	div->lock = lock;

	cname = devm_kasprintf(dev, GFP_KERNEL, "%s.%s",
			       of_node_full_name(dev->of_node), name);
	if (!cname)
		return -ENOMEM;

	/* Set clock direction */
	writel(dir_bit, base + div_reg);

	chw = devm_clk_hw_register_composite_pdata(dev, cname,
						   &pdata, 1, NULL, NULL,
						   &div->hw,
						   &clk_divider_ops,
						   &gate->hw,
						   &clk_gate_ops,
						   CLK_SET_RATE_GATE);
	if (IS_ERR(chw))
		return PTR_ERR(chw);

	*hw = chw;

	return 0;
}

static int fsl_sai_clk_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	const struct fsl_sai_data *data = device_get_match_data(dev);
	struct fsl_sai_clk *sai_clk;
	struct clk *clk_bus;
	void __iomem *base;
	int ret;

	sai_clk = devm_kzalloc(dev, sizeof(*sai_clk), GFP_KERNEL);
	if (!sai_clk)
		return -ENOMEM;

Annotation

Implementation Notes