drivers/clk/clk-hsdk-pll.c

Source file repositories/reference/linux-study-clean/drivers/clk/clk-hsdk-pll.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/clk-hsdk-pll.c
Extension
.c
Size
11025 bytes
Lines
430
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct hsdk_pll_cfg {
	u32 rate;
	u32 idiv;
	u32 fbdiv;
	u32 odiv;
	u32 band;
	u32 bypass;
};

static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
	{ 100000000,  0, 11, 3, 0, 0 },
	{ 133000000,  0, 15, 3, 0, 0 },
	{ 200000000,  1, 47, 3, 0, 0 },
	{ 233000000,  1, 27, 2, 0, 0 },
	{ 300000000,  1, 35, 2, 0, 0 },
	{ 333000000,  1, 39, 2, 0, 0 },
	{ 400000000,  1, 47, 2, 0, 0 },
	{ 500000000,  0, 14, 1, 0, 0 },
	{ 600000000,  0, 17, 1, 0, 0 },
	{ 700000000,  0, 20, 1, 0, 0 },
	{ 800000000,  0, 23, 1, 0, 0 },
	{ 900000000,  1, 26, 0, 0, 0 },
	{ 1000000000, 1, 29, 0, 0, 0 },
	{ 1100000000, 1, 32, 0, 0, 0 },
	{ 1200000000, 1, 35, 0, 0, 0 },
	{ 1300000000, 1, 38, 0, 0, 0 },
	{ 1400000000, 1, 41, 0, 0, 0 },
	{ 1500000000, 1, 44, 0, 0, 0 },
	{ 1600000000, 1, 47, 0, 0, 0 },
	{}
};

static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
	{ 27000000,   0, 0,  0, 0, 1 },
	{ 148500000,  0, 21, 3, 0, 0 },
	{ 297000000,  0, 21, 2, 0, 0 },
	{ 540000000,  0, 19, 1, 0, 0 },
	{ 594000000,  0, 21, 1, 0, 0 },
	{}
};

struct hsdk_pll_clk {
	struct clk_hw hw;
	void __iomem *regs;
	void __iomem *spec_regs;
	const struct hsdk_pll_devdata *pll_devdata;
	struct device *dev;
};

struct hsdk_pll_devdata {
	const struct hsdk_pll_cfg *pll_cfg;
	int (*update_rate)(struct hsdk_pll_clk *clk, unsigned long rate,
			   const struct hsdk_pll_cfg *cfg);
};

static int hsdk_pll_core_update_rate(struct hsdk_pll_clk *, unsigned long,
				     const struct hsdk_pll_cfg *);
static int hsdk_pll_comm_update_rate(struct hsdk_pll_clk *, unsigned long,
				     const struct hsdk_pll_cfg *);

static const struct hsdk_pll_devdata core_pll_devdata = {
	.pll_cfg = asdt_pll_cfg,
	.update_rate = hsdk_pll_core_update_rate,
};

static const struct hsdk_pll_devdata sdt_pll_devdata = {
	.pll_cfg = asdt_pll_cfg,
	.update_rate = hsdk_pll_comm_update_rate,
};

static const struct hsdk_pll_devdata hdmi_pll_devdata = {
	.pll_cfg = hdmi_pll_cfg,
	.update_rate = hsdk_pll_comm_update_rate,
};

static inline void hsdk_pll_write(struct hsdk_pll_clk *clk, u32 reg, u32 val)
{
	iowrite32(val, clk->regs + reg);
}

static inline u32 hsdk_pll_read(struct hsdk_pll_clk *clk, u32 reg)
{
	return ioread32(clk->regs + reg);
}

static inline void hsdk_pll_set_cfg(struct hsdk_pll_clk *clk,
				    const struct hsdk_pll_cfg *cfg)
{
	u32 val = 0;

Annotation

Implementation Notes