drivers/clk/clk-k210.c

Source file repositories/reference/linux-study-clean/drivers/clk/clk-k210.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/clk-k210.c
Extension
.c
Size
25520 bytes
Lines
1011
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct k210_clk {
	int id;
	struct k210_sysclk *ksc;
	struct clk_hw hw;
};

struct k210_clk_cfg {
	const char *name;
	u8 gate_reg;
	u8 gate_bit;
	u8 div_reg;
	u8 div_shift;
	u8 div_width;
	u8 div_type;
	u8 mux_reg;
	u8 mux_bit;
};

enum k210_clk_div_type {
	K210_DIV_NONE,
	K210_DIV_ONE_BASED,
	K210_DIV_DOUBLE_ONE_BASED,
	K210_DIV_POWER_OF_TWO,
};

#define K210_GATE(_reg, _bit)	\
	.gate_reg = (_reg),	\
	.gate_bit = (_bit)

#define K210_DIV(_reg, _shift, _width, _type)	\
	.div_reg = (_reg),			\
	.div_shift = (_shift),			\
	.div_width = (_width),			\
	.div_type = (_type)

#define K210_MUX(_reg, _bit)	\
	.mux_reg = (_reg),	\
	.mux_bit = (_bit)

static struct k210_clk_cfg k210_clk_cfgs[K210_NUM_CLKS] = {
	/* Gated clocks, no mux, no divider */
	[K210_CLK_CPU] = {
		.name = "cpu",
		K210_GATE(K210_SYSCTL_EN_CENT, 0)
	},
	[K210_CLK_DMA] = {
		.name = "dma",
		K210_GATE(K210_SYSCTL_EN_PERI, 1)
	},
	[K210_CLK_FFT] = {
		.name = "fft",
		K210_GATE(K210_SYSCTL_EN_PERI, 4)
	},
	[K210_CLK_GPIO] = {
		.name = "gpio",
		K210_GATE(K210_SYSCTL_EN_PERI, 5)
	},
	[K210_CLK_UART1] = {
		.name = "uart1",
		K210_GATE(K210_SYSCTL_EN_PERI, 16)
	},
	[K210_CLK_UART2] = {
		.name = "uart2",
		K210_GATE(K210_SYSCTL_EN_PERI, 17)
	},
	[K210_CLK_UART3] = {
		.name = "uart3",
		K210_GATE(K210_SYSCTL_EN_PERI, 18)
	},
	[K210_CLK_FPIOA] = {
		.name = "fpioa",
		K210_GATE(K210_SYSCTL_EN_PERI, 20)
	},
	[K210_CLK_SHA] = {
		.name = "sha",
		K210_GATE(K210_SYSCTL_EN_PERI, 26)
	},
	[K210_CLK_AES] = {
		.name = "aes",
		K210_GATE(K210_SYSCTL_EN_PERI, 19)
	},
	[K210_CLK_OTP] = {
		.name = "otp",
		K210_GATE(K210_SYSCTL_EN_PERI, 27)
	},
	[K210_CLK_RTC] = {
		.name = "rtc",
		K210_GATE(K210_SYSCTL_EN_PERI, 29)
	},

Annotation

Implementation Notes