drivers/clk/clk-max9485.c

Source file repositories/reference/linux-study-clean/drivers/clk/clk-max9485.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/clk-max9485.c
Extension
.c
Size
10150 bytes
Lines
394
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct max9485_rate {
	unsigned long out;
	u8 reg_value;
};

/*
 * Ordered by frequency. For frequency the hardware can generate with
 * multiple settings, the one with lowest jitter is listed first.
 */
static const struct max9485_rate max9485_rates[] = {
	{  3072000, MAX9485_FS_12KHZ   | MAX9485_SCALE_256 },
	{  4608000, MAX9485_FS_12KHZ   | MAX9485_SCALE_384 },
	{  8192000, MAX9485_FS_32KHZ   | MAX9485_SCALE_256 },
	{  9126000, MAX9485_FS_12KHZ   | MAX9485_SCALE_768 },
	{ 11289600, MAX9485_FS_44_1KHZ | MAX9485_SCALE_256 },
	{ 12288000, MAX9485_FS_48KHZ   | MAX9485_SCALE_256 },
	{ 12288000, MAX9485_FS_32KHZ   | MAX9485_SCALE_384 },
	{ 16384000, MAX9485_FS_32KHZ   | MAX9485_SCALE_256 | MAX9485_DOUBLE },
	{ 16934400, MAX9485_FS_44_1KHZ | MAX9485_SCALE_384 },
	{ 18384000, MAX9485_FS_48KHZ   | MAX9485_SCALE_384 },
	{ 22579200, MAX9485_FS_44_1KHZ | MAX9485_SCALE_256 | MAX9485_DOUBLE },
	{ 24576000, MAX9485_FS_48KHZ   | MAX9485_SCALE_256 | MAX9485_DOUBLE },
	{ 24576000, MAX9485_FS_32KHZ   | MAX9485_SCALE_384 | MAX9485_DOUBLE },
	{ 24576000, MAX9485_FS_32KHZ   | MAX9485_SCALE_768 },
	{ 33868800, MAX9485_FS_44_1KHZ | MAX9485_SCALE_384 | MAX9485_DOUBLE },
	{ 33868800, MAX9485_FS_44_1KHZ | MAX9485_SCALE_768 },
	{ 36864000, MAX9485_FS_48KHZ   | MAX9485_SCALE_384 | MAX9485_DOUBLE },
	{ 36864000, MAX9485_FS_48KHZ   | MAX9485_SCALE_768 },
	{ 49152000, MAX9485_FS_32KHZ   | MAX9485_SCALE_768 | MAX9485_DOUBLE },
	{ 67737600, MAX9485_FS_44_1KHZ | MAX9485_SCALE_768 | MAX9485_DOUBLE },
	{ 73728000, MAX9485_FS_48KHZ   | MAX9485_SCALE_768 | MAX9485_DOUBLE },
	{ } /* sentinel */
};

struct max9485_driver_data;

struct max9485_clk_hw {
	struct clk_hw hw;
	struct clk_init_data init;
	u8 enable_bit;
	struct max9485_driver_data *drvdata;
};

struct max9485_driver_data {
	struct clk *xclk;
	struct i2c_client *client;
	u8 reg_value;
	struct regulator *supply;
	struct gpio_desc *reset_gpio;
	struct max9485_clk_hw hw[MAX9485_NUM_CLKS];
};

static inline struct max9485_clk_hw *to_max9485_clk(struct clk_hw *hw)
{
	return container_of(hw, struct max9485_clk_hw, hw);
}

static int max9485_update_bits(struct max9485_driver_data *drvdata,
			       u8 mask, u8 value)
{
	int ret;

	drvdata->reg_value &= ~mask;
	drvdata->reg_value |= value;

	dev_dbg(&drvdata->client->dev,
		"updating mask 0x%02x value 0x%02x -> 0x%02x\n",
		mask, value, drvdata->reg_value);

	ret = i2c_master_send(drvdata->client,
			      &drvdata->reg_value,
			      sizeof(drvdata->reg_value));

	return ret < 0 ? ret : 0;
}

static int max9485_clk_prepare(struct clk_hw *hw)
{
	struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);

	return max9485_update_bits(clk_hw->drvdata,
				   clk_hw->enable_bit,
				   clk_hw->enable_bit);
}

static void max9485_clk_unprepare(struct clk_hw *hw)
{
	struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);

	max9485_update_bits(clk_hw->drvdata, clk_hw->enable_bit, 0);

Annotation

Implementation Notes