drivers/clk/clk-rp1.c
Source file repositories/reference/linux-study-clean/drivers/clk/clk-rp1.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/clk/clk-rp1.c- Extension
.c- Size
- 68620 bytes
- Lines
- 2463
- Domain
- Driver Families
- Bucket
- drivers/clk
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bitfield.hlinux/clk-provider.hlinux/regmap.hlinux/math64.hlinux/module.hlinux/platform_device.hlinux/units.hdt-bindings/clock/raspberrypi,rp1-clocks.h
Detected Declarations
struct rp1_clockmanstruct rp1_pll_core_datastruct rp1_pll_datastruct rp1_pll_ph_datastruct rp1_pll_divider_datastruct rp1_clock_datastruct rp1_clk_descfunction clockman_writefunction clockman_readfunction rp1_pll_core_is_onfunction rp1_pll_core_onfunction rp1_pll_core_offfunction get_pll_core_dividerfunction rp1_pll_core_set_ratefunction rp1_pll_core_recalc_ratefunction rp1_pll_core_determine_ratefunction get_pll_prim_dividersfunction rp1_pll_set_ratefunction rp1_pll_recalc_ratefunction rp1_pll_determine_ratefunction rp1_pll_ph_is_onfunction rp1_pll_ph_onfunction rp1_pll_ph_offfunction rp1_pll_ph_recalc_ratefunction rp1_pll_ph_determine_ratefunction rp1_pll_divider_is_onfunction rp1_pll_divider_onfunction rp1_pll_divider_offfunction rp1_pll_divider_set_ratefunction rp1_pll_divider_recalc_ratefunction rp1_pll_divider_determine_ratefunction rp1_clock_is_onfunction rp1_clock_recalc_ratefunction rp1_clock_onfunction rp1_clock_offfunction rp1_clock_choose_divfunction rp1_clock_get_parentfunction rp1_clock_set_parentfunction rp1_clock_set_rate_and_parentfunction rp1_clock_set_ratefunction calc_core_pll_ratefunction rp1_clock_choose_div_and_pratefunction rp1_clock_determine_ratefunction rp1_varsrc_set_ratefunction rp1_varsrc_recalc_ratefunction rp1_varsrc_determine_ratefunction rp1_clk_probe
Annotated Snippet
struct rp1_clockman {
struct device *dev;
void __iomem *regs;
struct regmap *regmap;
spinlock_t regs_lock; /* spinlock for all clocks */
/* Must be last */
struct clk_hw_onecell_data onecell;
};
struct rp1_pll_core_data {
u32 cs_reg;
u32 pwr_reg;
u32 fbdiv_int_reg;
u32 fbdiv_frac_reg;
u32 fc0_src;
};
struct rp1_pll_data {
u32 ctrl_reg;
u32 fc0_src;
};
struct rp1_pll_ph_data {
unsigned int phase;
unsigned int fixed_divider;
u32 ph_reg;
u32 fc0_src;
};
struct rp1_pll_divider_data {
u32 sec_reg;
u32 fc0_src;
};
struct rp1_clock_data {
int num_std_parents;
int num_aux_parents;
u32 oe_mask;
u32 clk_src_mask;
u32 ctrl_reg;
u32 div_int_reg;
u32 div_frac_reg;
u32 sel_reg;
u32 div_int_max;
unsigned long max_freq;
u32 fc0_src;
};
struct rp1_clk_desc {
struct clk_hw *(*clk_register)(struct rp1_clockman *clockman,
struct rp1_clk_desc *desc);
const void *data;
struct clk_hw hw;
struct rp1_clockman *clockman;
unsigned long cached_rate;
struct clk_divider div;
};
static struct rp1_clk_desc *clk_audio_core;
static struct rp1_clk_desc *clk_audio;
static struct rp1_clk_desc *clk_i2s;
static struct clk_hw *clk_xosc;
static inline
void clockman_write(struct rp1_clockman *clockman, u32 reg, u32 val)
{
regmap_write(clockman->regmap, reg, val);
}
static inline u32 clockman_read(struct rp1_clockman *clockman, u32 reg)
{
u32 val;
regmap_read(clockman->regmap, reg, &val);
return val;
}
static int rp1_pll_core_is_on(struct clk_hw *hw)
{
struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw);
struct rp1_clockman *clockman = pll_core->clockman;
const struct rp1_pll_core_data *data = pll_core->data;
u32 pwr = clockman_read(clockman, data->pwr_reg);
return (pwr & PLL_PWR_PD) || (pwr & PLL_PWR_POSTDIVPD);
}
static int rp1_pll_core_on(struct clk_hw *hw)
Annotation
- Immediate include surface: `linux/bitfield.h`, `linux/clk-provider.h`, `linux/regmap.h`, `linux/math64.h`, `linux/module.h`, `linux/platform_device.h`, `linux/units.h`, `dt-bindings/clock/raspberrypi,rp1-clocks.h`.
- Detected declarations: `struct rp1_clockman`, `struct rp1_pll_core_data`, `struct rp1_pll_data`, `struct rp1_pll_ph_data`, `struct rp1_pll_divider_data`, `struct rp1_clock_data`, `struct rp1_clk_desc`, `function clockman_write`, `function clockman_read`, `function rp1_pll_core_is_on`.
- Atlas domain: Driver Families / drivers/clk.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.