drivers/clk/clk-si5341.c

Source file repositories/reference/linux-study-clean/drivers/clk/clk-si5341.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/clk-si5341.c
Extension
.c
Size
47987 bytes
Lines
1861
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct clk_si5341_synth {
	struct clk_hw hw;
	struct clk_si5341 *data;
	u8 index;
};
#define to_clk_si5341_synth(_hw) \
	container_of(_hw, struct clk_si5341_synth, hw)

/* The output stages can be connected to any synth (full mux) */
struct clk_si5341_output {
	struct clk_hw hw;
	struct clk_si5341 *data;
	struct regulator *vddo_reg;
	u8 index;
};
#define to_clk_si5341_output(_hw) \
	container_of(_hw, struct clk_si5341_output, hw)

struct clk_si5341 {
	struct clk_hw hw;
	struct regmap *regmap;
	struct i2c_client *i2c_client;
	struct clk_si5341_synth synth[SI5341_NUM_SYNTH];
	struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS];
	struct clk *input_clk[SI5341_NUM_INPUTS];
	const char *input_clk_name[SI5341_NUM_INPUTS];
	const u16 *reg_output_offset;
	const u16 *reg_rdiv_offset;
	u64 freq_vco; /* 13500–14256 MHz */
	u8 num_outputs;
	u8 num_synth;
	u16 chip_id;
	bool xaxb_ext_clk;
	bool iovdd_33;
};
#define to_clk_si5341(_hw)	container_of(_hw, struct clk_si5341, hw)

struct clk_si5341_output_config {
	u8 out_format_drv_bits;
	u8 out_cm_ampl_bits;
	u8 vdd_sel_bits;
	bool synth_master;
	bool always_on;
};

#define SI5341_PAGE		0x0001
#define SI5341_PN_BASE		0x0002
#define SI5341_DEVICE_REV	0x0005
#define SI5341_STATUS		0x000C
#define SI5341_LOS		0x000D
#define SI5341_STATUS_STICKY	0x0011
#define SI5341_LOS_STICKY	0x0012
#define SI5341_SOFT_RST		0x001C
#define SI5341_IN_SEL		0x0021
#define SI5341_DEVICE_READY	0x00FE
#define SI5341_XAXB_CFG		0x090E
#define SI5341_IO_VDD_SEL	0x0943
#define SI5341_IN_EN		0x0949
#define SI5341_INX_TO_PFD_EN	0x094A

/* Status bits */
#define SI5341_STATUS_SYSINCAL	BIT(0)
#define SI5341_STATUS_LOSXAXB	BIT(1)
#define SI5341_STATUS_LOSREF	BIT(2)
#define SI5341_STATUS_LOL	BIT(3)

/* Input selection */
#define SI5341_IN_SEL_MASK	0x06
#define SI5341_IN_SEL_SHIFT	1
#define SI5341_IN_SEL_REGCTRL	0x01
#define SI5341_INX_TO_PFD_SHIFT	4

/* XTAL config bits */
#define SI5341_XAXB_CFG_EXTCLK_EN	BIT(0)
#define SI5341_XAXB_CFG_PDNB		BIT(1)

/* Input dividers (48-bit) */
#define SI5341_IN_PDIV(x)	(0x0208 + ((x) * 10))
#define SI5341_IN_PSET(x)	(0x020E + ((x) * 10))
#define SI5341_PX_UPD		0x0230

/* PLL configuration */
#define SI5341_PLL_M_NUM	0x0235
#define SI5341_PLL_M_DEN	0x023B

/* Output configuration */
#define SI5341_OUT_CONFIG(output)	\
			((output)->data->reg_output_offset[(output)->index])
#define SI5341_OUT_FORMAT(output)	(SI5341_OUT_CONFIG(output) + 1)
#define SI5341_OUT_CM(output)		(SI5341_OUT_CONFIG(output) + 2)

Annotation

Implementation Notes