drivers/clk/clk-sp7021.c
Source file repositories/reference/linux-study-clean/drivers/clk/clk-sp7021.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/clk/clk-sp7021.c- Extension
.c- Size
- 15748 bytes
- Lines
- 709
- Domain
- Driver Families
- Bucket
- drivers/clk
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/module.hlinux/clk-provider.hlinux/of.hlinux/bitfield.hlinux/hw_bitfield.hlinux/slab.hlinux/io.hlinux/err.hlinux/platform_device.hdt-bindings/clock/sunplus,sp7021-clkc.h
Detected Declarations
struct sp_pllstruct sp_clk_gate_infofunction plltv_integer_divfunction plltv_fractional_divfunction plltv_divfunction plltv_set_ratefunction plla_set_ratefunction plla_round_ratefunction sp_pll_calc_divfunction sp_pll_determine_ratefunction sp_pll_recalc_ratefunction sp_pll_set_ratefunction sp_pll_enablefunction sp_pll_disablefunction sp_pll_is_enabledfunction sp7021_clk_probe
Annotated Snippet
struct sp_pll {
struct clk_hw hw;
void __iomem *reg;
spinlock_t lock; /* lock for reg */
int div_shift;
int div_width;
int pd_bit; /* power down bit idx */
int bp_bit; /* bypass bit idx */
unsigned long brate; /* base rate, TODO: replace brate with muldiv */
u32 p[P_MAX]; /* for hold PLLTV/PLLA parameters */
};
#define to_sp_pll(_hw) container_of(_hw, struct sp_pll, hw)
struct sp_clk_gate_info {
u16 reg; /* reg_index_shift */
u16 ext_parent; /* parent is extclk */
};
static const struct sp_clk_gate_info sp_clk_gates[] = {
{ 0x02 },
{ 0x05 },
{ 0x06 },
{ 0x07 },
{ 0x09 },
{ 0x0b, 1 },
{ 0x0f, 1 },
{ 0x14 },
{ 0x15 },
{ 0x16 },
{ 0x17 },
{ 0x18, 1 },
{ 0x19, 1 },
{ 0x1a, 1 },
{ 0x1b, 1 },
{ 0x1c, 1 },
{ 0x1d, 1 },
{ 0x1e },
{ 0x1f, 1 },
{ 0x20 },
{ 0x21 },
{ 0x22 },
{ 0x23 },
{ 0x24 },
{ 0x25 },
{ 0x26 },
{ 0x2a },
{ 0x2b },
{ 0x2d },
{ 0x2e },
{ 0x30 },
{ 0x31 },
{ 0x32 },
{ 0x33 },
{ 0x3d },
{ 0x3e },
{ 0x3f },
{ 0x42 },
{ 0x44 },
{ 0x4b },
{ 0x4c },
{ 0x4d },
{ 0x4e },
{ 0x4f },
{ 0x50 },
{ 0x55 },
{ 0x60 },
{ 0x61 },
{ 0x6a },
{ 0x73 },
{ 0x86 },
{ 0x8a },
{ 0x8b },
{ 0x8d },
{ 0x8e },
{ 0x8f },
{ 0x90 },
{ 0x92 },
{ 0x93 },
{ 0x95 },
{ 0x96 },
{ 0x97 },
{ 0x98 },
{ 0x99 },
};
#define _M 1000000UL
#define F_27M (27 * _M)
/*********************************** PLL_TV **********************************/
Annotation
- Immediate include surface: `linux/module.h`, `linux/clk-provider.h`, `linux/of.h`, `linux/bitfield.h`, `linux/hw_bitfield.h`, `linux/slab.h`, `linux/io.h`, `linux/err.h`.
- Detected declarations: `struct sp_pll`, `struct sp_clk_gate_info`, `function plltv_integer_div`, `function plltv_fractional_div`, `function plltv_div`, `function plltv_set_rate`, `function plla_set_rate`, `function plla_round_rate`, `function sp_pll_calc_div`, `function sp_pll_determine_rate`.
- Atlas domain: Driver Families / drivers/clk.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.