drivers/clk/clk_test.c
Source file repositories/reference/linux-study-clean/drivers/clk/clk_test.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/clk/clk_test.c- Extension
.c- Size
- 102450 bytes
- Lines
- 3566
- Domain
- Driver Families
- Bucket
- drivers/clk
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/clk.hlinux/clk-provider.hlinux/clk/clk-conf.hlinux/of.hlinux/platform_device.hclk.hkunit/clk.hkunit/of.hkunit/platform_device.hkunit/test.hkunit_clk_assigned_rates.hclk_parent_data_test.h
Detected Declarations
struct clk_dummy_contextstruct clk_multiple_parent_ctxstruct clk_single_parent_ctxstruct clk_single_parent_two_lvl_ctxstruct clk_leaf_mux_ctxstruct clk_leaf_mux_set_rate_parent_determine_rate_test_casestruct clk_mux_notifier_rate_changestruct clk_mux_notifier_ctxstruct clk_register_clk_parent_data_test_casestruct clk_register_clk_parent_data_of_ctxstruct platform_driver_dev_ctxstruct clk_assigned_rates_contextstruct clk_assigned_rates_test_paramfunction clk_dummy_recalc_ratefunction clk_dummy_determine_ratefunction clk_dummy_maximize_ratefunction clk_dummy_minimize_ratefunction clk_dummy_set_ratefunction clk_dummy_single_set_parentfunction clk_dummy_single_get_parentfunction clk_multiple_parents_mux_set_parentfunction clk_multiple_parents_mux_get_parentfunction clk_test_init_with_opsfunction clk_test_initfunction clk_maximize_test_initfunction clk_minimize_test_initfunction clk_test_exitfunction clk_get_ratefunction clk_get_ratefunction clk_get_ratefunction clk_test_round_set_get_ratefunction clk_uncached_test_initfunction clk_get_ratefunction clk_test_uncached_set_rangefunction clk_test_uncached_updated_rate_set_rangefunction clk_multiple_parents_mux_test_initfunction clk_test_multiple_parents_mux_get_parentfunction clk_test_multiple_parents_mux_has_parentfunction clk_test_multiple_parents_mux_set_range_set_parent_get_ratefunction clk_orphan_transparent_multiple_parent_mux_test_initfunction clk_test_orphan_transparent_multiple_parent_mux_get_parentfunction clk_set_parentfunction clk_test_orphan_transparent_multiple_parent_mux_set_parent_drop_rangefunction clk_test_orphan_transparent_multiple_parent_mux_set_parent_get_ratefunction clk_test_orphan_transparent_multiple_parent_mux_set_parent_putfunction clk_test_orphan_transparent_multiple_parent_mux_set_parent_set_range_modifiedfunction clk_test_orphan_transparent_multiple_parent_mux_set_parent_set_range_untouchedfunction clk_set_rate_range
Annotated Snippet
struct clk_dummy_context {
struct clk_hw hw;
unsigned long rate;
};
static unsigned long clk_dummy_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_dummy_context *ctx =
container_of(hw, struct clk_dummy_context, hw);
return ctx->rate;
}
static int clk_dummy_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
/* Just return the same rate without modifying it */
return 0;
}
static int clk_dummy_maximize_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
/*
* If there's a maximum set, always run the clock at the maximum
* allowed.
*/
if (req->max_rate < ULONG_MAX)
req->rate = req->max_rate;
return 0;
}
static int clk_dummy_minimize_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
/*
* If there's a minimum set, always run the clock at the minimum
* allowed.
*/
if (req->min_rate > 0)
req->rate = req->min_rate;
return 0;
}
static int clk_dummy_set_rate(struct clk_hw *hw,
unsigned long rate,
unsigned long parent_rate)
{
struct clk_dummy_context *ctx =
container_of(hw, struct clk_dummy_context, hw);
ctx->rate = rate;
return 0;
}
static int clk_dummy_single_set_parent(struct clk_hw *hw, u8 index)
{
if (index >= clk_hw_get_num_parents(hw))
return -EINVAL;
return 0;
}
static u8 clk_dummy_single_get_parent(struct clk_hw *hw)
{
return 0;
}
static const struct clk_ops clk_dummy_rate_ops = {
.recalc_rate = clk_dummy_recalc_rate,
.determine_rate = clk_dummy_determine_rate,
.set_rate = clk_dummy_set_rate,
};
static const struct clk_ops clk_dummy_maximize_rate_ops = {
.recalc_rate = clk_dummy_recalc_rate,
.determine_rate = clk_dummy_maximize_rate,
.set_rate = clk_dummy_set_rate,
};
static const struct clk_ops clk_dummy_minimize_rate_ops = {
.recalc_rate = clk_dummy_recalc_rate,
.determine_rate = clk_dummy_minimize_rate,
.set_rate = clk_dummy_set_rate,
};
static const struct clk_ops clk_dummy_single_parent_ops = {
Annotation
- Immediate include surface: `linux/clk.h`, `linux/clk-provider.h`, `linux/clk/clk-conf.h`, `linux/of.h`, `linux/platform_device.h`, `clk.h`, `kunit/clk.h`, `kunit/of.h`.
- Detected declarations: `struct clk_dummy_context`, `struct clk_multiple_parent_ctx`, `struct clk_single_parent_ctx`, `struct clk_single_parent_two_lvl_ctx`, `struct clk_leaf_mux_ctx`, `struct clk_leaf_mux_set_rate_parent_determine_rate_test_case`, `struct clk_mux_notifier_rate_change`, `struct clk_mux_notifier_ctx`, `struct clk_register_clk_parent_data_test_case`, `struct clk_register_clk_parent_data_of_ctx`.
- Atlas domain: Driver Families / drivers/clk.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.