drivers/clk/clk-versaclock3.c

Source file repositories/reference/linux-study-clean/drivers/clk/clk-versaclock3.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/clk-versaclock3.c
Extension
.c
Size
29375 bytes
Lines
1169
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct vc3_clk_data {
	u8 offs;
	u8 bitmsk;
};

struct vc3_pfd_data {
	u8 num;
	u8 offs;
	u8 mdiv1_bitmsk;
	u8 mdiv2_bitmsk;
};

struct vc3_vco {
	unsigned long min;
	unsigned long max;
};

struct vc3_pll_data {
	struct vc3_vco vco;
	u8 num;
	u8 int_div_msb_offs;
	u8 int_div_lsb_offs;
};

struct vc3_div_data {
	const struct clk_div_table *table;
	u8 offs;
	u8 shift;
	u8 width;
	u8 flags;
};

struct vc3_hw_data {
	struct clk_hw hw;
	struct regmap *regmap;
	void *data;

	u32 div_int;
	u32 div_frc;
};

struct vc3_hw_cfg {
	struct vc3_vco pll2_vco;
	u32 se2_clk_sel_msk;
};

static const struct clk_div_table div1_divs[] = {
	{ .val = 0, .div = 1, }, { .val = 1, .div = 4, },
	{ .val = 2, .div = 5, }, { .val = 3, .div = 6, },
	{ .val = 4, .div = 2, }, { .val = 5, .div = 8, },
	{ .val = 6, .div = 10, }, { .val = 7, .div = 12, },
	{ .val = 8, .div = 4, }, { .val = 9, .div = 16, },
	{ .val = 10, .div = 20, }, { .val = 11, .div = 24, },
	{ .val = 12, .div = 8, }, { .val = 13, .div = 32, },
	{ .val = 14, .div = 40, }, { .val = 15, .div = 48, },
	{}
};

static const struct clk_div_table div245_divs[] = {
	{ .val = 0, .div = 1, }, { .val = 1, .div = 3, },
	{ .val = 2, .div = 5, }, { .val = 3, .div = 10, },
	{ .val = 4, .div = 2, }, { .val = 5, .div = 6, },
	{ .val = 6, .div = 10, }, { .val = 7, .div = 20, },
	{ .val = 8, .div = 4, }, { .val = 9, .div = 12, },
	{ .val = 10, .div = 20, }, { .val = 11, .div = 40, },
	{ .val = 12, .div = 5, }, { .val = 13, .div = 15, },
	{ .val = 14, .div = 25, }, { .val = 15, .div = 50, },
	{}
};

static const struct clk_div_table div3_divs[] = {
	{ .val = 0, .div = 1, }, { .val = 1, .div = 3, },
	{ .val = 2, .div = 5, }, { .val = 3, .div = 10, },
	{ .val = 4, .div = 2, }, { .val = 5, .div = 6, },
	{ .val = 6, .div = 10, }, { .val = 7, .div = 20, },
	{ .val = 8, .div = 4, }, { .val = 9, .div = 12, },
	{ .val = 10, .div = 20, }, { .val = 11, .div = 40, },
	{ .val = 12, .div = 8, }, { .val = 13, .div = 24, },
	{ .val = 14, .div = 40, }, { .val = 15, .div = 80, },
	{}
};

static struct clk_hw *clk_out[6];

static u8 vc3_pfd_mux_get_parent(struct clk_hw *hw)
{
	struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
	const struct vc3_clk_data *pfd_mux = vc3->data;
	u32 src;

Annotation

Implementation Notes