drivers/clk/eswin/clk.c

Source file repositories/reference/linux-study-clean/drivers/clk/eswin/clk.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/eswin/clk.c
Extension
.c
Size
14882 bytes
Lines
587
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

switch (info->type) {
		case CLK_FIXED_FACTOR: {
			const struct eswin_fixed_factor_clock *factor;

			factor = &info->data.factor;
			phw = data->clk_data.hws[info->pid];
			hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, factor->name, phw,
									 factor->flags,
									 factor->mult,
									 factor->div);
			break;
		}
		case CLK_MUX: {
			const struct eswin_mux_clock *mux = &info->data.mux;

			hw = devm_clk_hw_register_mux_parent_data_table(dev, mux->name,
									mux->parent_data,
									mux->num_parents,
									mux->flags,
									data->base + mux->reg,
									mux->shift, mux->width,
									mux->mux_flags,
									mux->table, &data->lock);
			break;
		}
		case CLK_DIVIDER: {
			const struct eswin_divider_clock *div = &info->data.div;

			phw = data->clk_data.hws[info->pid];
			if (div->priv_flag)
				hw = eswin_register_clkdiv(dev, div->id, div->name, phw,
							   div->flags, data->base + div->reg,
							   div->shift, div->width, div->div_flags,
							   div->priv_flag, &data->lock);
			else
				hw = devm_clk_hw_register_divider_parent_hw(dev, div->name, phw,
									    div->flags,
									    data->base + div->reg,
									    div->shift, div->width,
									    div->div_flags,
									    &data->lock);
			break;
		}
		case CLK_GATE: {
			const struct eswin_gate_clock *gate = &info->data.gate;

			phw = data->clk_data.hws[info->pid];
			hw = devm_clk_hw_register_gate_parent_hw(dev, gate->name, phw,
								 gate->flags,
								 data->base + gate->reg,
								 gate->bit_idx, gate->gate_flags,
								 &data->lock);
			break;
		}
		default:
			dev_err(dev, "Unidentifiable clock type!\n");
			return -EINVAL;
		}
		if (IS_ERR(hw))
			return PTR_ERR(hw);

		info->hw = *hw;
		data->clk_data.hws[info->id] = hw;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(eswin_clk_register_clks);

Annotation

Implementation Notes