drivers/clk/eswin/clk-eic7700.c

Source file repositories/reference/linux-study-clean/drivers/clk/eswin/clk-eic7700.c

File Facts

System: Linux kernel
Corpus path: drivers/clk/eswin/clk-eic7700.c
Extension: .c
Size: 62265 bytes
Lines: 1377
Domain: Driver Families
Bucket: drivers/clk
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

linux/clk.h
linux/clk-provider.h
linux/platform_device.h
dt-bindings/clock/eswin,eic7700-clock.h
common.h

Detected Declarations

function eic7700_clk_pll_cpu_notifier_cb
function eic7700_clk_probe

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
 * All rights reserved.
 *
 * ESWIN EIC7700 Clk Provider Driver
 *
 * Authors:
 *	Yifeng Huang <huangyifeng@eswincomputing.com>
 *	Xuyang Dong <dongxuyang@eswincomputing.com>
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>

#include <dt-bindings/clock/eswin,eic7700-clock.h>

#include "common.h"

/* REG OFFSET OF SYS-CRG */
#define EIC7700_REG_OFFSET_SPLL0_CFG_0		0x0
#define EIC7700_REG_OFFSET_SPLL0_CFG_1		0x4
#define EIC7700_REG_OFFSET_SPLL0_CFG_2		0x8
#define EIC7700_REG_OFFSET_SPLL0_DSKEWCAL	0xC
#define EIC7700_REG_OFFSET_SPLL0_SSC		0x10
#define EIC7700_REG_OFFSET_SPLL1_CFG_0		0x14
#define EIC7700_REG_OFFSET_SPLL1_CFG_1		0x18
#define EIC7700_REG_OFFSET_SPLL1_CFG_2		0x1C
#define EIC7700_REG_OFFSET_SPLL1_DSKEWCAL	0x20
#define EIC7700_REG_OFFSET_SPLL1_SSC		0x24
#define EIC7700_REG_OFFSET_SPLL2_CFG_0		0x28
#define EIC7700_REG_OFFSET_SPLL2_CFG_1		0x2C
#define EIC7700_REG_OFFSET_SPLL2_CFG_2		0x30
#define EIC7700_REG_OFFSET_SPLL2_DSKEWCAL	0x34
#define EIC7700_REG_OFFSET_SPLL2_SSC		0x38
#define EIC7700_REG_OFFSET_VPLL_CFG_0		0x3C
#define EIC7700_REG_OFFSET_VPLL_CFG_1		0x40
#define EIC7700_REG_OFFSET_VPLL_CFG_2		0x44
#define EIC7700_REG_OFFSET_VPLL_DSKEWCAL	0x48
#define EIC7700_REG_OFFSET_VPLL_SSC		0x4C
#define EIC7700_REG_OFFSET_APLL_CFG_0		0x50
#define EIC7700_REG_OFFSET_APLL_CFG_1		0x54
#define EIC7700_REG_OFFSET_APLL_CFG_2		0x58
#define EIC7700_REG_OFFSET_APLL_DSKEWCAL	0x5C
#define EIC7700_REG_OFFSET_APLL_SSC		0x60
#define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_0	0x64
#define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_1	0x68
#define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_2	0x6C
#define EIC7700_REG_OFFSET_MCPUT_PLL_DSKEWCAL	0x70
#define EIC7700_REG_OFFSET_MCPUT_PLL_SSC	0x74
#define EIC7700_REG_OFFSET_DDRT_PLL_CFG_0	0x78
#define EIC7700_REG_OFFSET_DDRT_PLL_CFG_1	0x7C
#define EIC7700_REG_OFFSET_DDRT_PLL_CFG_2	0x80
#define EIC7700_REG_OFFSET_DDRT_PLL_DSKEWCAL	0x84
#define EIC7700_REG_OFFSET_DDRT_PLL_SSC		0x88
#define EIC7700_REG_OFFSET_PLL_STATUS		0xA4
#define EIC7700_REG_OFFSET_NOC			0x100
#define EIC7700_REG_OFFSET_BOOTSPI		0x104
#define EIC7700_REG_OFFSET_BOOTSPI_CFGCLK	0x108
#define EIC7700_REG_OFFSET_SCPU_CORE		0x10C
#define EIC7700_REG_OFFSET_SCPU_BUSCLK		0x110
#define EIC7700_REG_OFFSET_LPCPU_CORE		0x114
#define EIC7700_REG_OFFSET_LPCPU_BUSCLK		0x118
#define EIC7700_REG_OFFSET_TCU_ACLK		0x11C
#define EIC7700_REG_OFFSET_TCU_CFG		0x120
#define EIC7700_REG_OFFSET_DDR			0x124
#define EIC7700_REG_OFFSET_DDR1			0x128
#define EIC7700_REG_OFFSET_GPU_ACLK		0x12C
#define EIC7700_REG_OFFSET_GPU_CFG		0x130
#define EIC7700_REG_OFFSET_GPU_GRAY		0x134
#define EIC7700_REG_OFFSET_DSP_ACLK		0x138
#define EIC7700_REG_OFFSET_DSP_CFG		0x13C
#define EIC7700_REG_OFFSET_D2D_ACLK		0x140
#define EIC7700_REG_OFFSET_D2D_CFG		0x144
#define EIC7700_REG_OFFSET_HSP_ACLK		0x148
#define EIC7700_REG_OFFSET_HSP_CFG		0x14C
#define EIC7700_REG_OFFSET_SATA_RBC		0x150
#define EIC7700_REG_OFFSET_SATA_OOB		0x154
#define EIC7700_REG_OFFSET_ETH0			0x158
#define EIC7700_REG_OFFSET_ETH1			0x15C
#define EIC7700_REG_OFFSET_MSHC0_CORE		0x160
#define EIC7700_REG_OFFSET_MSHC1_CORE		0x164
#define EIC7700_REG_OFFSET_MSHC2_CORE		0x168
#define EIC7700_REG_OFFSET_MSHC_USB_SLWCLK	0x16C
#define EIC7700_REG_OFFSET_PCIE_ACLK		0x170
#define EIC7700_REG_OFFSET_PCIE_CFG		0x174
#define EIC7700_REG_OFFSET_NPU_ACLK		0x178
#define EIC7700_REG_OFFSET_NPU_LLC		0x17C
#define EIC7700_REG_OFFSET_NPU_CORE		0x180

Annotation

Immediate include surface: `linux/clk.h`, `linux/clk-provider.h`, `linux/platform_device.h`, `dt-bindings/clock/eswin,eic7700-clock.h`, `common.h`.
Detected declarations: `function eic7700_clk_pll_cpu_notifier_cb`, `function eic7700_clk_probe`.
Atlas domain: Driver Families / drivers/clk.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.