drivers/clk/hisilicon/clk-hi6220.c

Source file repositories/reference/linux-study-clean/drivers/clk/hisilicon/clk-hi6220.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/hisilicon/clk-hi6220.c
Extension
.c
Size
19291 bytes
Lines
305
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Hisilicon Hi6220 clock driver
 *
 * Copyright (c) 2015 Hisilicon Limited.
 *
 * Author: Bintian Wang <bintian.wang@huawei.com>
 */

#include <linux/kernel.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/io.h>
#include <linux/slab.h>

#include <dt-bindings/clock/hi6220-clock.h>

#include "clk.h"


/* clocks in AO (always on) controller */
static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
	{ HI6220_REF32K,	"ref32k",	NULL, 0, 32764,     },
	{ HI6220_CLK_TCXO,	"clk_tcxo",	NULL, 0, 19200000,  },
	{ HI6220_MMC1_PAD,	"mmc1_pad",	NULL, 0, 100000000, },
	{ HI6220_MMC2_PAD,	"mmc2_pad",	NULL, 0, 100000000, },
	{ HI6220_MMC0_PAD,	"mmc0_pad",	NULL, 0, 200000000, },
	{ HI6220_PLL_BBP,	"bbppll0",	NULL, 0, 245760000, },
	{ HI6220_PLL_GPU,	"gpupll",	NULL, 0, 1000000000,},
	{ HI6220_PLL1_DDR,	"ddrpll1",	NULL, 0, 1066000000,},
	{ HI6220_PLL_SYS,	"syspll",	NULL, 0, 1190400000,},
	{ HI6220_PLL_SYS_MEDIA,	"media_syspll",	NULL, 0, 1190400000,},
	{ HI6220_DDR_SRC,	"ddr_sel_src",  NULL, 0, 1200000000,},
	{ HI6220_PLL_MEDIA,	"media_pll",    NULL, 0, 1440000000,},
	{ HI6220_PLL_DDR,	"ddrpll0",      NULL, 0, 1600000000,},
};

static struct hisi_fixed_factor_clock hi6220_fixed_factor_clks[] __initdata = {
	{ HI6220_300M,         "clk_300m",    "syspll",          1, 4, 0, },
	{ HI6220_150M,         "clk_150m",    "clk_300m",        1, 2, 0, },
	{ HI6220_PICOPHY_SRC,  "picophy_src", "clk_150m",        1, 4, 0, },
	{ HI6220_MMC0_SRC_SEL, "mmc0srcsel",  "mmc0_sel",        1, 8, 0, },
	{ HI6220_MMC1_SRC_SEL, "mmc1srcsel",  "mmc1_sel",        1, 8, 0, },
	{ HI6220_MMC2_SRC_SEL, "mmc2srcsel",  "mmc2_sel",        1, 8, 0, },
	{ HI6220_VPU_CODEC,    "vpucodec",    "codec_jpeg_aclk", 1, 2, 0, },
	{ HI6220_MMC0_SMP,     "mmc0_sample", "mmc0_sel",        1, 8, 0, },
	{ HI6220_MMC1_SMP,     "mmc1_sample", "mmc1_sel",        1, 8, 0, },
	{ HI6220_MMC2_SMP,     "mmc2_sample", "mmc2_sel",        1, 8, 0, },
};

static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = {
	{ HI6220_WDT0_PCLK,   "wdt0_pclk",   "ref32k",   CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 12, 0, },
	{ HI6220_WDT1_PCLK,   "wdt1_pclk",   "ref32k",   CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 13, 0, },
	{ HI6220_WDT2_PCLK,   "wdt2_pclk",   "ref32k",   CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 14, 0, },
	{ HI6220_TIMER0_PCLK, "timer0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 15, 0, },
	{ HI6220_TIMER1_PCLK, "timer1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 16, 0, },
	{ HI6220_TIMER2_PCLK, "timer2_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 17, 0, },
	{ HI6220_TIMER3_PCLK, "timer3_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 18, 0, },
	{ HI6220_TIMER4_PCLK, "timer4_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 19, 0, },
	{ HI6220_TIMER5_PCLK, "timer5_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 20, 0, },
	{ HI6220_TIMER6_PCLK, "timer6_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 21, 0, },
	{ HI6220_TIMER7_PCLK, "timer7_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 22, 0, },
	{ HI6220_TIMER8_PCLK, "timer8_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 23, 0, },
	{ HI6220_UART0_PCLK,  "uart0_pclk",  "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 24, 0, },
	{ HI6220_RTC0_PCLK,   "rtc0_pclk",   "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 25, 0, },
	{ HI6220_RTC1_PCLK,   "rtc1_pclk",   "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 26, 0, },
};

static void __init hi6220_clk_ao_init(struct device_node *np)
{
	struct hisi_clock_data *clk_data_ao;

	clk_data_ao = hisi_clk_init(np, HI6220_AO_NR_CLKS);
	if (!clk_data_ao)
		return;

	hisi_clk_register_fixed_rate(hi6220_fixed_rate_clks,
				ARRAY_SIZE(hi6220_fixed_rate_clks), clk_data_ao);

	hisi_clk_register_fixed_factor(hi6220_fixed_factor_clks,
				ARRAY_SIZE(hi6220_fixed_factor_clks), clk_data_ao);

	hisi_clk_register_gate_sep(hi6220_separated_gate_clks_ao,
				ARRAY_SIZE(hi6220_separated_gate_clks_ao), clk_data_ao);
}
/* Allow reset driver to probe as well */
CLK_OF_DECLARE_DRIVER(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_init);


/* clocks in sysctrl */

Annotation

Implementation Notes