drivers/clk/imx/clk-fixup-mux.c
Source file repositories/reference/linux-study-clean/drivers/clk/imx/clk-fixup-mux.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/clk/imx/clk-fixup-mux.c- Extension
.c- Size
- 2497 bytes
- Lines
- 108
- Domain
- Driver Families
- Bucket
- drivers/clk
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bits.hlinux/clk-provider.hlinux/err.hlinux/io.hlinux/slab.hclk.h
Detected Declarations
struct clk_fixup_muxfunction clk_fixup_mux_get_parentfunction clk_fixup_mux_set_parent
Annotated Snippet
struct clk_fixup_mux {
struct clk_mux mux;
const struct clk_ops *ops;
void (*fixup)(u32 *val);
};
static inline struct clk_fixup_mux *to_clk_fixup_mux(struct clk_hw *hw)
{
struct clk_mux *mux = to_clk_mux(hw);
return container_of(mux, struct clk_fixup_mux, mux);
}
static u8 clk_fixup_mux_get_parent(struct clk_hw *hw)
{
struct clk_fixup_mux *fixup_mux = to_clk_fixup_mux(hw);
return fixup_mux->ops->get_parent(&fixup_mux->mux.hw);
}
static int clk_fixup_mux_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_fixup_mux *fixup_mux = to_clk_fixup_mux(hw);
struct clk_mux *mux = to_clk_mux(hw);
unsigned long flags;
u32 val;
spin_lock_irqsave(mux->lock, flags);
val = readl(mux->reg);
val &= ~(mux->mask << mux->shift);
val |= index << mux->shift;
fixup_mux->fixup(&val);
writel(val, mux->reg);
spin_unlock_irqrestore(mux->lock, flags);
return 0;
}
static const struct clk_ops clk_fixup_mux_ops = {
.determine_rate = clk_hw_determine_rate_no_reparent,
.get_parent = clk_fixup_mux_get_parent,
.set_parent = clk_fixup_mux_set_parent,
};
struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg,
u8 shift, u8 width, const char * const *parents,
int num_parents, void (*fixup)(u32 *val))
{
struct clk_fixup_mux *fixup_mux;
struct clk_hw *hw;
struct clk_init_data init;
int ret;
if (!fixup)
return ERR_PTR(-EINVAL);
fixup_mux = kzalloc_obj(*fixup_mux);
if (!fixup_mux)
return ERR_PTR(-ENOMEM);
init.name = name;
init.ops = &clk_fixup_mux_ops;
init.parent_names = parents;
init.num_parents = num_parents;
init.flags = 0;
fixup_mux->mux.reg = reg;
fixup_mux->mux.shift = shift;
fixup_mux->mux.mask = BIT(width) - 1;
fixup_mux->mux.lock = &imx_ccm_lock;
fixup_mux->mux.hw.init = &init;
fixup_mux->ops = &clk_mux_ops;
fixup_mux->fixup = fixup;
hw = &fixup_mux->mux.hw;
ret = clk_hw_register(NULL, hw);
if (ret) {
kfree(fixup_mux);
return ERR_PTR(ret);
}
return hw;
}
Annotation
- Immediate include surface: `linux/bits.h`, `linux/clk-provider.h`, `linux/err.h`, `linux/io.h`, `linux/slab.h`, `clk.h`.
- Detected declarations: `struct clk_fixup_mux`, `function clk_fixup_mux_get_parent`, `function clk_fixup_mux_set_parent`.
- Atlas domain: Driver Families / drivers/clk.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.