drivers/clk/imx/clk.h

Source file repositories/reference/linux-study-clean/drivers/clk/imx/clk.h

File Facts

System
Linux kernel
Corpus path
drivers/clk/imx/clk.h
Extension
.h
Size
17275 bytes
Lines
491
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct imx_pll14xx_rate_table {
	unsigned int rate;
	unsigned int pdiv;
	unsigned int mdiv;
	unsigned int sdiv;
	unsigned int kdiv;
};

struct imx_pll14xx_clk {
	enum imx_pll14xx_type type;
	const struct imx_pll14xx_rate_table *rate_table;
	int rate_count;
	int flags;
};

extern struct imx_pll14xx_clk imx_1416x_pll;
extern struct imx_pll14xx_clk imx_1443x_pll;
extern struct imx_pll14xx_clk imx_1443x_dram_pll;

#define CLK_FRACN_GPPLL_INTEGER	BIT(0)
#define CLK_FRACN_GPPLL_FRACN	BIT(1)

/* NOTE: Rate table should be kept sorted in descending order. */
struct imx_fracn_gppll_rate_table {
	unsigned int rate;
	unsigned int mfi;
	unsigned int mfn;
	unsigned int mfd;
	unsigned int rdiv;
	unsigned int odiv;
};

struct imx_fracn_gppll_clk {
	const struct imx_fracn_gppll_rate_table *rate_table;
	int rate_count;
	int flags;
};

struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base,
				   const struct imx_fracn_gppll_clk *pll_clk);
struct clk_hw *imx_clk_fracn_gppll_integer(const char *name, const char *parent_name,
					   void __iomem *base,
					   const struct imx_fracn_gppll_clk *pll_clk);

extern struct imx_fracn_gppll_clk imx_fracn_gppll;
extern struct imx_fracn_gppll_clk imx_fracn_gppll_integer;

#define imx_clk_cpu(name, parent_name, div, mux, pll, step) \
	to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))

#define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
				cgr_val, cgr_mask, clk_gate_flags, lock, share_count) \
	to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
				cgr_val, cgr_mask, clk_gate_flags, lock, share_count))

#define imx_clk_pllv3(type, name, parent_name, base, div_mask) \
	to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))

#define imx_clk_pfd(name, parent_name, reg, idx) \
	to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))

#define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \
	to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))

#define imx_clk_fixed(name, rate) \
	to_clk(imx_clk_hw_fixed(name, rate))

#define imx_clk_fixed_factor(name, parent, mult, div) \
	to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div))

#define imx_clk_divider(name, parent, reg, shift, width) \
	to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))

#define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \
	to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))

#define imx_clk_gate(name, parent, reg, shift) \
	to_clk(imx_clk_hw_gate(name, parent, reg, shift))

#define imx_clk_gate_dis(name, parent, reg, shift) \
	to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))

#define imx_clk_gate2(name, parent, reg, shift) \
	to_clk(imx_clk_hw_gate2(name, parent, reg, shift))

#define imx_clk_gate2_cgr(name, parent, reg, shift, cgr_val) \
	to_clk(__imx_clk_hw_gate2(name, parent, reg, shift, cgr_val, 0, NULL))

#define imx_clk_gate2_flags(name, parent, reg, shift, flags) \
	to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))

Annotation

Implementation Notes