drivers/clk/imx/clk-imx5.c

Source file repositories/reference/linux-study-clean/drivers/clk/imx/clk-imx5.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/imx/clk-imx5.c
Extension
.c
Size
36344 bytes
Lines
615
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
 */
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/sizes.h>
#include <soc/imx/revision.h>
#include <dt-bindings/clock/imx5-clock.h>

#include "clk.h"

#define MX51_DPLL1_BASE		0x83f80000
#define MX51_DPLL2_BASE		0x83f84000
#define MX51_DPLL3_BASE		0x83f88000

#define MX53_DPLL1_BASE		0x63f80000
#define MX53_DPLL2_BASE		0x63f84000
#define MX53_DPLL3_BASE		0x63f88000
#define MX53_DPLL4_BASE		0x63f8c000

#define MXC_CCM_CCR		(ccm_base + 0x00)
#define MXC_CCM_CCDR		(ccm_base + 0x04)
#define MXC_CCM_CSR		(ccm_base + 0x08)
#define MXC_CCM_CCSR		(ccm_base + 0x0c)
#define MXC_CCM_CACRR		(ccm_base + 0x10)
#define MXC_CCM_CBCDR		(ccm_base + 0x14)
#define MXC_CCM_CBCMR		(ccm_base + 0x18)
#define MXC_CCM_CSCMR1		(ccm_base + 0x1c)
#define MXC_CCM_CSCMR2		(ccm_base + 0x20)
#define MXC_CCM_CSCDR1		(ccm_base + 0x24)
#define MXC_CCM_CS1CDR		(ccm_base + 0x28)
#define MXC_CCM_CS2CDR		(ccm_base + 0x2c)
#define MXC_CCM_CDCDR		(ccm_base + 0x30)
#define MXC_CCM_CHSCDR		(ccm_base + 0x34)
#define MXC_CCM_CSCDR2		(ccm_base + 0x38)
#define MXC_CCM_CSCDR3		(ccm_base + 0x3c)
#define MXC_CCM_CSCDR4		(ccm_base + 0x40)
#define MXC_CCM_CWDR		(ccm_base + 0x44)
#define MXC_CCM_CDHIPR		(ccm_base + 0x48)
#define MXC_CCM_CDCR		(ccm_base + 0x4c)
#define MXC_CCM_CTOR		(ccm_base + 0x50)
#define MXC_CCM_CLPCR		(ccm_base + 0x54)
#define MXC_CCM_CISR		(ccm_base + 0x58)
#define MXC_CCM_CIMR		(ccm_base + 0x5c)
#define MXC_CCM_CCOSR		(ccm_base + 0x60)
#define MXC_CCM_CGPR		(ccm_base + 0x64)
#define MXC_CCM_CCGR0		(ccm_base + 0x68)
#define MXC_CCM_CCGR1		(ccm_base + 0x6c)
#define MXC_CCM_CCGR2		(ccm_base + 0x70)
#define MXC_CCM_CCGR3		(ccm_base + 0x74)
#define MXC_CCM_CCGR4		(ccm_base + 0x78)
#define MXC_CCM_CCGR5		(ccm_base + 0x7c)
#define MXC_CCM_CCGR6		(ccm_base + 0x80)
#define MXC_CCM_CCGR7		(ccm_base + 0x84)

/* Low-power Audio Playback Mode clock */
static const char *lp_apm_sel[] = { "osc", };

/* This is used multiple times */
static const char *standard_pll_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "lp_apm", };
static const char *periph_apm_sel[] = { "pll1_sw", "pll3_sw", "lp_apm", };
static const char *main_bus_sel[] = { "pll2_sw", "periph_apm", };
static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", };
static const char *per_root_sel[] = { "per_podf", "ipg", };
static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
static const char *ssi_apm_sels[] = { "ckih1", "lp_amp", "ckih2", };
static const char *ssi_clk_sels[] = { "pll1_sw", "pll2_sw", "pll3_sw", "ssi_apm", };
static const char *ssi3_clk_sels[] = { "ssi1_root_gate", "ssi2_root_gate", };
static const char *ssi_ext1_com_sels[] = { "ssi_ext1_podf", "ssi1_root_gate", };
static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", };
static const char *emi_slow_sel[] = { "main_bus", "ahb", };
static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", };
static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", };
static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };

Annotation

Implementation Notes