drivers/clk/imx/clk-imx7d.c

Source file repositories/reference/linux-study-clean/drivers/clk/imx/clk-imx7d.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/imx/clk-imx7d.c
Extension
.c
Size
66703 bytes
Lines
888
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
 */

#include <dt-bindings/clock/imx7d-clock.h>
#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/types.h>

#include "clk.h"

static u32 share_count_sai1;
static u32 share_count_sai2;
static u32 share_count_sai3;
static u32 share_count_nand;
static u32 share_count_enet1;
static u32 share_count_enet2;

static const struct clk_div_table test_div_table[] = {
	{ .val = 3, .div = 1, },
	{ .val = 2, .div = 1, },
	{ .val = 1, .div = 2, },
	{ .val = 0, .div = 4, },
	{ }
};

static const struct clk_div_table post_div_table[] = {
	{ .val = 3, .div = 4, },
	{ .val = 2, .div = 1, },
	{ .val = 1, .div = 2, },
	{ .val = 0, .div = 1, },
	{ }
};

static const char *arm_a7_sel[] = { "osc", "pll_arm_main_clk",
	"pll_enet_500m_clk", "pll_dram_main_clk",
	"pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_audio_post_div",
	"pll_usb_main_clk", };

static const char *arm_m4_sel[] = { "osc", "pll_sys_main_240m_clk",
	"pll_enet_250m_clk", "pll_sys_pfd2_270m_clk",
	"pll_dram_533m_clk", "pll_audio_post_div", "pll_video_post_div",
	"pll_usb_main_clk", };

static const char *axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
	"pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd5_clk",
	"pll_audio_post_div", "pll_video_post_div", "pll_sys_pfd7_clk", };

static const char *disp_axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
	"pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd6_clk",
	"pll_sys_pfd7_clk", "pll_audio_post_div", "pll_video_post_div", };

static const char *enet_axi_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
	"pll_dram_533m_clk", "pll_enet_250m_clk",
	"pll_sys_main_240m_clk", "pll_audio_post_div", "pll_video_post_div",
	"pll_sys_pfd4_clk", };

static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
	"pll_dram_533m_clk", "pll_sys_main_240m_clk",
	"pll_sys_pfd2_135m_clk", "pll_sys_pfd6_clk", "pll_enet_250m_clk",
	"pll_audio_post_div", };

static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
	"pll_dram_533m_clk", "pll_sys_pfd0_392m_clk",
	"pll_enet_250m_clk", "pll_usb_main_clk", "pll_audio_post_div",
	"pll_video_post_div", };

static const char *dram_phym_sel[] = { "pll_dram_main_clk",
	"dram_phym_alt_clk", };

static const char *dram_sel[] = { "pll_dram_main_clk",
	"dram_alt_root_clk", };

static const char *dram_phym_alt_sel[] = { "osc", "pll_dram_533m_clk",
	"pll_sys_main_clk", "pll_enet_500m_clk",
	"pll_usb_main_clk", "pll_sys_pfd7_clk", "pll_audio_post_div",
	"pll_video_post_div", };

static const char *dram_alt_sel[] = { "osc", "pll_dram_533m_clk",
	"pll_sys_main_clk", "pll_enet_500m_clk",
	"pll_enet_250m_clk", "pll_sys_pfd0_392m_clk",

Annotation

Implementation Notes