drivers/clk/imx/clk-imx8-acm.c

Source file repositories/reference/linux-study-clean/drivers/clk/imx/clk-imx8-acm.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/imx/clk-imx8-acm.c
Extension
.c
Size
17162 bytes
Lines
499
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct clk_imx_acm_pm_domains {
	struct device **pd_dev;
	struct device_link **pd_dev_link;
	int    num_domains;
};

/**
 * struct clk_imx8_acm_sel - for clock mux
 * @name: clock name
 * @clkid: clock id
 * @parents: clock parents
 * @num_parents: clock parents number
 * @reg: register offset
 * @shift: bit shift in register
 * @width: bits width
 */
struct clk_imx8_acm_sel {
	const char			*name;
	int				clkid;
	const struct clk_parent_data	*parents;	/* For mux */
	int				num_parents;
	u32				reg;
	u8				shift;
	u8				width;
};

/**
 * struct imx8_acm_soc_data - soc specific data
 * @sels: pointer to struct clk_imx8_acm_sel
 * @num_sels: numbers of items
 * @mclk_sels: pointer to imx8qm/qxp/dxl_mclk_sels
 */
struct imx8_acm_soc_data {
	struct clk_imx8_acm_sel *sels;
	unsigned int num_sels;
	struct clk_parent_data *mclk_sels;
};

/**
 * struct imx8_acm_priv - private structure
 * @dev_pm: multi power domain
 * @soc_data: pointer to soc data
 * @reg: base address of registers
 * @regs: save registers for suspend
 */
struct imx8_acm_priv {
	struct clk_imx_acm_pm_domains dev_pm;
	const struct imx8_acm_soc_data *soc_data;
	void __iomem *reg;
	u32 regs[IMX_ADMA_ACM_CLK_END];
};

static const struct clk_parent_data imx8qm_aud_clk_sels[] = {
	{ .fw_name = "aud_rec_clk0_lpcg_clk" },
	{ .fw_name = "aud_rec_clk1_lpcg_clk" },
	{ .fw_name = "dummy" },
	{ .fw_name = "hdmi_rx_mclk" },
	{ .fw_name = "ext_aud_mclk0" },
	{ .fw_name = "ext_aud_mclk1" },
	{ .fw_name = "esai0_rx_clk" },
	{ .fw_name = "esai0_rx_hf_clk" },
	{ .fw_name = "esai0_tx_clk" },
	{ .fw_name = "esai0_tx_hf_clk" },
	{ .fw_name = "esai1_rx_clk" },
	{ .fw_name = "esai1_rx_hf_clk" },
	{ .fw_name = "esai1_tx_clk" },
	{ .fw_name = "esai1_tx_hf_clk" },
	{ .fw_name = "spdif0_rx" },
	{ .fw_name = "spdif1_rx" },
	{ .fw_name = "sai0_rx_bclk" },
	{ .fw_name = "sai0_tx_bclk" },
	{ .fw_name = "sai1_rx_bclk" },
	{ .fw_name = "sai1_tx_bclk" },
	{ .fw_name = "sai2_rx_bclk" },
	{ .fw_name = "sai3_rx_bclk" },
	{ .fw_name = "sai4_rx_bclk" },
};

static const struct clk_parent_data imx8qm_mclk_out_sels[] = {
	{ .fw_name = "aud_rec_clk0_lpcg_clk" },
	{ .fw_name = "aud_rec_clk1_lpcg_clk" },
	{ .fw_name = "dummy" },
	{ .fw_name = "hdmi_rx_mclk" },
	{ .fw_name = "spdif0_rx" },
	{ .fw_name = "spdif1_rx" },
	{ .fw_name = "sai4_rx_bclk" },
	{ .fw_name = "sai6_rx_bclk" },
};

#define ACM_AUD_CLK0_SEL_INDEX  2

Annotation

Implementation Notes