drivers/clk/imx/clk-imx8mp.c

File Facts

System

Linux kernel

Corpus path

drivers/clk/imx/clk-imx8mp.c

Extension

.c

Size

56711 bytes

Lines

906

Domain

Driver Families

Bucket

drivers/clk

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Allocates kernel memory; connect allocation flags and lifetime to context constraints.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• dt-bindings/clock/imx8mp-clock.h
• linux/clk-provider.h
• linux/err.h
• linux/io.h
• linux/module.h
• linux/units.h
• linux/of_address.h
• linux/platform_device.h
• linux/slab.h
• linux/types.h
• clk.h

Detected Declarations

• struct imx8mp_clock_constraints
• function imx8mp_clocks_apply_constraints
• function imx8mp_clocks_probe

Annotated Snippet

struct imx8mp_clock_constraints {
	unsigned int clkid;
	u32 maxrate;
};

/*
 * Below tables are taken from IMX8MPCEC Rev. 2.1, 07/2023
 * Table 13. Maximum frequency of modules.
 * Probable typos fixed are marked with a comment.
 */
static const struct imx8mp_clock_constraints imx8mp_clock_common_constraints[] = {
	{ IMX8MP_CLK_A53_DIV,             1000 * HZ_PER_MHZ },
	{ IMX8MP_CLK_ENET_AXI,             266666667 }, /* Datasheet claims 266MHz */
	{ IMX8MP_CLK_NAND_USDHC_BUS,       266666667 }, /* Datasheet claims 266MHz */
	{ IMX8MP_CLK_MEDIA_APB,            200 * HZ_PER_MHZ },
	{ IMX8MP_CLK_HDMI_APB,             133333333 }, /* Datasheet claims 133MHz */
	{ IMX8MP_CLK_ML_AXI,               800 * HZ_PER_MHZ },
	{ IMX8MP_CLK_AHB,                  133333333 },
	{ IMX8MP_CLK_IPG_ROOT,              66666667 },
	{ IMX8MP_CLK_AUDIO_AHB,            400 * HZ_PER_MHZ },
	{ IMX8MP_CLK_MEDIA_DISP2_PIX,      170 * HZ_PER_MHZ },
	{ IMX8MP_CLK_DRAM_ALT,             666666667 },
	{ IMX8MP_CLK_DRAM_APB,             200 * HZ_PER_MHZ },
	{ IMX8MP_CLK_CAN1,                  80 * HZ_PER_MHZ },
	{ IMX8MP_CLK_CAN2,                  80 * HZ_PER_MHZ },
	{ IMX8MP_CLK_PCIE_AUX,              10 * HZ_PER_MHZ },
	{ IMX8MP_CLK_I2C5,                  66666667 }, /* Datasheet claims 66MHz */
	{ IMX8MP_CLK_I2C6,                  66666667 }, /* Datasheet claims 66MHz */
	{ IMX8MP_CLK_SAI1,                  66666667 }, /* Datasheet claims 66MHz */
	{ IMX8MP_CLK_SAI2,                  66666667 }, /* Datasheet claims 66MHz */
	{ IMX8MP_CLK_SAI3,                  66666667 }, /* Datasheet claims 66MHz */
	{ IMX8MP_CLK_SAI5,                  66666667 }, /* Datasheet claims 66MHz */
	{ IMX8MP_CLK_SAI6,                  66666667 }, /* Datasheet claims 66MHz */
	{ IMX8MP_CLK_ENET_QOS,             125 * HZ_PER_MHZ },
	{ IMX8MP_CLK_ENET_QOS_TIMER,       200 * HZ_PER_MHZ },
	{ IMX8MP_CLK_ENET_REF,             125 * HZ_PER_MHZ },
	{ IMX8MP_CLK_ENET_TIMER,           125 * HZ_PER_MHZ },
	{ IMX8MP_CLK_ENET_PHY_REF,         125 * HZ_PER_MHZ },
	{ IMX8MP_CLK_NAND,                 500 * HZ_PER_MHZ },
	{ IMX8MP_CLK_QSPI,                 400 * HZ_PER_MHZ },
	{ IMX8MP_CLK_USDHC1,               400 * HZ_PER_MHZ },
	{ IMX8MP_CLK_USDHC2,               400 * HZ_PER_MHZ },
	{ IMX8MP_CLK_I2C1,                  66666667 }, /* Datasheet claims 66MHz */
	{ IMX8MP_CLK_I2C2,                  66666667 }, /* Datasheet claims 66MHz */
	{ IMX8MP_CLK_I2C3,                  66666667 }, /* Datasheet claims 66MHz */
	{ IMX8MP_CLK_I2C4,                  66666667 }, /* Datasheet claims 66MHz */
	{ IMX8MP_CLK_UART1,                 80 * HZ_PER_MHZ },
	{ IMX8MP_CLK_UART2,                 80 * HZ_PER_MHZ },
	{ IMX8MP_CLK_UART3,                 80 * HZ_PER_MHZ },
	{ IMX8MP_CLK_UART4,                 80 * HZ_PER_MHZ },
	{ IMX8MP_CLK_ECSPI1,                80 * HZ_PER_MHZ },
	{ IMX8MP_CLK_ECSPI2,                80 * HZ_PER_MHZ },
	{ IMX8MP_CLK_PWM1,                  66666667 }, /* Datasheet claims 66MHz */
	{ IMX8MP_CLK_PWM2,                  66666667 }, /* Datasheet claims 66MHz */
	{ IMX8MP_CLK_PWM3,                  66666667 }, /* Datasheet claims 66MHz */
	{ IMX8MP_CLK_PWM4,                  66666667 }, /* Datasheet claims 66MHz */
	{ IMX8MP_CLK_GPT1,                 100 * HZ_PER_MHZ },
	{ IMX8MP_CLK_GPT2,                 100 * HZ_PER_MHZ },
	{ IMX8MP_CLK_GPT3,                 100 * HZ_PER_MHZ },
	{ IMX8MP_CLK_GPT4,                 100 * HZ_PER_MHZ },
	{ IMX8MP_CLK_GPT5,                 100 * HZ_PER_MHZ },
	{ IMX8MP_CLK_GPT6,                 100 * HZ_PER_MHZ },
	{ IMX8MP_CLK_WDOG,                  66666667 }, /* Datasheet claims 66MHz */
	{ IMX8MP_CLK_IPP_DO_CLKO1,         200 * HZ_PER_MHZ },
	{ IMX8MP_CLK_IPP_DO_CLKO2,         200 * HZ_PER_MHZ },
	{ IMX8MP_CLK_HDMI_REF_266M,        266 * HZ_PER_MHZ },
	{ IMX8MP_CLK_USDHC3,               400 * HZ_PER_MHZ },
	{ IMX8MP_CLK_MEDIA_MIPI_PHY1_REF,  300 * HZ_PER_MHZ },
	{ IMX8MP_CLK_MEDIA_DISP1_PIX,      250 * HZ_PER_MHZ },
	{ IMX8MP_CLK_MEDIA_CAM2_PIX,       277 * HZ_PER_MHZ },
	{ IMX8MP_CLK_MEDIA_LDB,            595 * HZ_PER_MHZ },
	{ IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE, 200 * HZ_PER_MHZ },
	{ IMX8MP_CLK_ECSPI3,                80 * HZ_PER_MHZ },
	{ IMX8MP_CLK_PDM,                  200 * HZ_PER_MHZ },
	{ IMX8MP_CLK_SAI7,                  66666667 }, /* Datasheet claims 66MHz */
	{ IMX8MP_CLK_MAIN_AXI,             400 * HZ_PER_MHZ },
	{ /* Sentinel */ }
};

static const struct imx8mp_clock_constraints imx8mp_clock_nominal_constraints[] = {
	{ IMX8MP_CLK_M7_CORE,           600 * HZ_PER_MHZ },
	{ IMX8MP_CLK_ML_CORE,           800 * HZ_PER_MHZ },
	{ IMX8MP_CLK_GPU3D_CORE,        800 * HZ_PER_MHZ },
	{ IMX8MP_CLK_GPU3D_SHADER_CORE, 800 * HZ_PER_MHZ },
	{ IMX8MP_CLK_GPU2D_CORE,        800 * HZ_PER_MHZ },
	{ IMX8MP_CLK_AUDIO_AXI_SRC,     600 * HZ_PER_MHZ },
	{ IMX8MP_CLK_HSIO_AXI,          400 * HZ_PER_MHZ },
	{ IMX8MP_CLK_MEDIA_ISP,         400 * HZ_PER_MHZ },
	{ IMX8MP_CLK_VPU_BUS,           600 * HZ_PER_MHZ },
	{ IMX8MP_CLK_MEDIA_AXI,         400 * HZ_PER_MHZ },

Annotation

• Immediate include surface: `dt-bindings/clock/imx8mp-clock.h`, `linux/clk-provider.h`, `linux/err.h`, `linux/io.h`, `linux/module.h`, `linux/units.h`, `linux/of_address.h`, `linux/platform_device.h`.
• Detected declarations: `struct imx8mp_clock_constraints`, `function imx8mp_clocks_apply_constraints`, `function imx8mp_clocks_probe`.
• Atlas domain: Driver Families / drivers/clk.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.