drivers/clk/imx/clk-imx8ulp.c

Source file repositories/reference/linux-study-clean/drivers/clk/imx/clk-imx8ulp.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/imx/clk-imx8ulp.c
Extension
.c
Size
35613 bytes
Lines
571
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct pcc_reset_dev {
	void __iomem *base;
	struct reset_controller_dev rcdev;
	const u32 *resets;
	/* Set to imx_ccm_lock to protect register access shared with clock control */
	spinlock_t *lock;
};

#define PCC_SW_RST	BIT(28)
#define to_pcc_reset_dev(_rcdev)	container_of(_rcdev, struct pcc_reset_dev, rcdev)

static const u32 pcc3_resets[] = {
	0xa8, 0xac, 0xc8, 0xcc, 0xd0,
	0xd4, 0xd8, 0xdc, 0xe0, 0xe4,
	0xe8, 0xec, 0xf0
};

static const u32 pcc4_resets[] = {
	0x4, 0x8, 0xc, 0x10, 0x14,
	0x18, 0x1c, 0x20, 0x24, 0x34,
	0x38, 0x3c, 0x40, 0x44, 0x48,
	0x4c, 0x54
};

static const u32 pcc5_resets[] = {
	0xa0, 0xa4, 0xa8, 0xac, 0xb0,
	0xb4, 0xbc, 0xc0, 0xc8, 0xcc,
	0xd0, 0xf0, 0xf4, 0xf8
};

static int imx8ulp_pcc_assert(struct reset_controller_dev *rcdev, unsigned long id)
{
	struct pcc_reset_dev *pcc_reset = to_pcc_reset_dev(rcdev);
	u32 offset = pcc_reset->resets[id];
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(pcc_reset->lock, flags);

	val = readl(pcc_reset->base + offset);
	val &= ~PCC_SW_RST;
	writel(val, pcc_reset->base + offset);

	spin_unlock_irqrestore(pcc_reset->lock, flags);

	return 0;
}

static int imx8ulp_pcc_deassert(struct reset_controller_dev *rcdev, unsigned long id)
{
	struct pcc_reset_dev *pcc_reset = to_pcc_reset_dev(rcdev);
	u32 offset = pcc_reset->resets[id];
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(pcc_reset->lock, flags);

	val = readl(pcc_reset->base + offset);
	val |= PCC_SW_RST;
	writel(val, pcc_reset->base + offset);

	spin_unlock_irqrestore(pcc_reset->lock, flags);

	return 0;
}

static const struct reset_control_ops imx8ulp_pcc_reset_ops = {
	.assert = imx8ulp_pcc_assert,
	.deassert = imx8ulp_pcc_deassert,
};

static int imx8ulp_pcc_reset_init(struct platform_device *pdev, void __iomem *base,
	 const u32 *resets, unsigned int nr_resets)
{
	struct device_node *np = pdev->dev.of_node;
	struct device *dev = &pdev->dev;
	struct pcc_reset_dev *pcc_reset;

	pcc_reset = devm_kzalloc(dev, sizeof(*pcc_reset), GFP_KERNEL);
	if (!pcc_reset)
		return -ENOMEM;

	pcc_reset->base = base;
	pcc_reset->lock = &imx_ccm_lock;
	pcc_reset->resets = resets;
	pcc_reset->rcdev.owner = THIS_MODULE;
	pcc_reset->rcdev.nr_resets = nr_resets;
	pcc_reset->rcdev.ops = &imx8ulp_pcc_reset_ops;
	pcc_reset->rcdev.of_node = np;

Annotation

Implementation Notes