drivers/clk/imx/clk-lpcg-scu.c

Source file repositories/reference/linux-study-clean/drivers/clk/imx/clk-lpcg-scu.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/imx/clk-lpcg-scu.c
Extension
.c
Size
4374 bytes
Lines
191
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct clk_lpcg_scu {
	struct clk_hw hw;
	void __iomem *reg;
	u8 bit_idx;
	bool hw_gate;

	/* for state save&restore */
	u32 state;
};

#define to_clk_lpcg_scu(_hw) container_of(_hw, struct clk_lpcg_scu, hw)

/* e10858 -LPCG clock gating register synchronization errata */
static void lpcg_e10858_writel(unsigned long rate, void __iomem *reg, u32 val)
{
	writel(val, reg);

	if (rate >= 24 * HZ_PER_MHZ || rate == 0) {
		/*
		 * The time taken to access the LPCG registers from the AP core
		 * through the interconnect is longer than the minimum delay
		 * of 4 clock cycles required by the errata.
		 * Adding a readl will provide sufficient delay to prevent
		 * back-to-back writes.
		 */
		readl(reg);
	} else {
		/*
		 * For clocks running below 24MHz, wait a minimum of
		 * 4 clock cycles.
		 */
		ndelay(4 * (DIV_ROUND_UP(1000 * HZ_PER_MHZ, rate)));
	}
}

static int clk_lpcg_scu_enable(struct clk_hw *hw)
{
	struct clk_lpcg_scu *clk = to_clk_lpcg_scu(hw);
	unsigned long flags;
	u32 reg, val;

	spin_lock_irqsave(&imx_lpcg_scu_lock, flags);

	reg = readl_relaxed(clk->reg);
	reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx);

	val = CLK_GATE_SCU_LPCG_SW_SEL;
	if (clk->hw_gate)
		val |= CLK_GATE_SCU_LPCG_HW_SEL;

	reg |= val << clk->bit_idx;

	lpcg_e10858_writel(clk_hw_get_rate(hw), clk->reg, reg);

	spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags);

	return 0;
}

static void clk_lpcg_scu_disable(struct clk_hw *hw)
{
	struct clk_lpcg_scu *clk = to_clk_lpcg_scu(hw);
	unsigned long flags;
	u32 reg;

	spin_lock_irqsave(&imx_lpcg_scu_lock, flags);

	reg = readl_relaxed(clk->reg);
	reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx);
	lpcg_e10858_writel(clk_hw_get_rate(hw), clk->reg, reg);

	spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags);
}

static const struct clk_ops clk_lpcg_scu_ops = {
	.enable = clk_lpcg_scu_enable,
	.disable = clk_lpcg_scu_disable,
};

struct clk_hw *__imx_clk_lpcg_scu(struct device *dev, const char *name,
				  const char *parent_name, unsigned long flags,
				  void __iomem *reg, u8 bit_idx, bool hw_gate)
{
	struct clk_lpcg_scu *clk;
	struct clk_init_data init;
	struct clk_hw *hw;
	int ret;

	clk = kzalloc_obj(*clk);
	if (!clk)

Annotation

Implementation Notes