drivers/clk/imx/clk-vf610.c
Source file repositories/reference/linux-study-clean/drivers/clk/imx/clk-vf610.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/clk/imx/clk-vf610.c- Extension
.c- Size
- 27001 bytes
- Lines
- 489
- Domain
- Driver Families
- Bucket
- drivers/clk
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/of_address.hlinux/bits.hlinux/clk.hlinux/syscore_ops.hdt-bindings/clock/vf610-clock.hclk.h
Detected Declarations
function vf610_get_fixed_clockfunction vf610_clk_suspendfunction vf610_clk_resumefunction vf610_clocks_init
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2012-2013 Freescale Semiconductor, Inc.
*/
#include <linux/of_address.h>
#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/syscore_ops.h>
#include <dt-bindings/clock/vf610-clock.h>
#include "clk.h"
/*
* The VF610_CLK_END corresponds to ones defined in
* include/dt-bindings/clock/vf610-clock.h
* It shall be the value of the last defined clock +1
*/
#define VF610_CLK_END 196
#define CCM_CCR (ccm_base + 0x00)
#define CCM_CSR (ccm_base + 0x04)
#define CCM_CCSR (ccm_base + 0x08)
#define CCM_CACRR (ccm_base + 0x0c)
#define CCM_CSCMR1 (ccm_base + 0x10)
#define CCM_CSCDR1 (ccm_base + 0x14)
#define CCM_CSCDR2 (ccm_base + 0x18)
#define CCM_CSCDR3 (ccm_base + 0x1c)
#define CCM_CSCMR2 (ccm_base + 0x20)
#define CCM_CSCDR4 (ccm_base + 0x24)
#define CCM_CLPCR (ccm_base + 0x2c)
#define CCM_CISR (ccm_base + 0x30)
#define CCM_CIMR (ccm_base + 0x34)
#define CCM_CGPR (ccm_base + 0x3c)
#define CCM_CCGR0 (ccm_base + 0x40)
#define CCM_CCGR1 (ccm_base + 0x44)
#define CCM_CCGR2 (ccm_base + 0x48)
#define CCM_CCGR3 (ccm_base + 0x4c)
#define CCM_CCGR4 (ccm_base + 0x50)
#define CCM_CCGR5 (ccm_base + 0x54)
#define CCM_CCGR6 (ccm_base + 0x58)
#define CCM_CCGR7 (ccm_base + 0x5c)
#define CCM_CCGR8 (ccm_base + 0x60)
#define CCM_CCGR9 (ccm_base + 0x64)
#define CCM_CCGR10 (ccm_base + 0x68)
#define CCM_CCGR11 (ccm_base + 0x6c)
#define CCM_CCGRx(x) (CCM_CCGR0 + (x) * 4)
#define CCM_CMEOR0 (ccm_base + 0x70)
#define CCM_CMEOR1 (ccm_base + 0x74)
#define CCM_CMEOR2 (ccm_base + 0x78)
#define CCM_CMEOR3 (ccm_base + 0x7c)
#define CCM_CMEOR4 (ccm_base + 0x80)
#define CCM_CMEOR5 (ccm_base + 0x84)
#define CCM_CPPDSR (ccm_base + 0x88)
#define CCM_CCOWR (ccm_base + 0x8c)
#define CCM_CCPGR0 (ccm_base + 0x90)
#define CCM_CCPGR1 (ccm_base + 0x94)
#define CCM_CCPGR2 (ccm_base + 0x98)
#define CCM_CCPGR3 (ccm_base + 0x9c)
#define CCM_CCGRx_CGn(n) ((n) * 2)
#define PFD_PLL1_BASE (anatop_base + 0x2b0)
#define PFD_PLL2_BASE (anatop_base + 0x100)
#define PFD_PLL3_BASE (anatop_base + 0xf0)
#define PLL1_CTRL (anatop_base + 0x270)
#define PLL2_CTRL (anatop_base + 0x30)
#define PLL3_CTRL (anatop_base + 0x10)
#define PLL4_CTRL (anatop_base + 0x70)
#define PLL5_CTRL (anatop_base + 0xe0)
#define PLL6_CTRL (anatop_base + 0xa0)
#define PLL7_CTRL (anatop_base + 0x20)
#define ANA_MISC1 (anatop_base + 0x160)
static void __iomem *anatop_base;
static void __iomem *ccm_base;
/* sources for multiplexer clocks, this is used multiple times */
static const char *fast_sels[] = { "firc", "fxosc", };
static const char *slow_sels[] = { "sirc_32k", "sxosc", };
static const char *pll1_sels[] = { "pll1_sys", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", };
static const char *pll2_sels[] = { "pll2_bus", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", };
static const char *pll_bypass_src_sels[] = { "fast_clk_sel", "lvds1_in", };
static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
Annotation
- Immediate include surface: `linux/of_address.h`, `linux/bits.h`, `linux/clk.h`, `linux/syscore_ops.h`, `dt-bindings/clock/vf610-clock.h`, `clk.h`.
- Detected declarations: `function vf610_get_fixed_clock`, `function vf610_clk_suspend`, `function vf610_clk_resume`, `function vf610_clocks_init`.
- Atlas domain: Driver Families / drivers/clk.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.