drivers/clk/ingenic/cgu.h

Source file repositories/reference/linux-study-clean/drivers/clk/ingenic/cgu.h

File Facts

System
Linux kernel
Corpus path
drivers/clk/ingenic/cgu.h
Extension
.h
Size
8285 bytes
Lines
247
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ingenic_cgu_pll_info {
	unsigned reg;
	unsigned rate_multiplier;
	const s8 *od_encoding;
	u8 m_shift, m_bits, m_offset;
	u8 n_shift, n_bits, n_offset;
	u8 od_shift, od_bits, od_max;
	unsigned bypass_reg;
	s8 bypass_bit;
	s8 enable_bit;
	s8 stable_bit;
	void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info,
			    unsigned long rate, unsigned long parent_rate,
			    unsigned int *m, unsigned int *n, unsigned int *od);
	void (*set_rate_hook)(const struct ingenic_cgu_pll_info *pll_info,
			      unsigned long rate, unsigned long parent_rate);
};

/**
 * struct ingenic_cgu_mux_info - information about a clock mux
 * @reg: offset of the mux control register within the CGU
 * @shift: number of bits to shift the mux value by (ie. the index of
 *         the lowest bit of the mux value within its control register)
 * @bits: the size of the mux value in bits
 */
struct ingenic_cgu_mux_info {
	unsigned reg;
	u8 shift;
	u8 bits;
};

/**
 * struct ingenic_cgu_div_info - information about a divider
 * @reg: offset of the divider control register within the CGU
 * @shift: number of bits to left shift the divide value by (ie. the index of
 *         the lowest bit of the divide value within its control register)
 * @div: number to divide the divider value by (i.e. if the
 *	 effective divider value is the value written to the register
 *	 multiplied by some constant)
 * @bits: the size of the divide value in bits
 * @ce_bit: the index of the change enable bit within reg, or -1 if there
 *          isn't one
 * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one
 * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one
 * @bypass_mask: mask of parent clocks for which the divider does not apply
 * @div_table: optional table to map the value read from the register to the
 *             actual divider value
 */
struct ingenic_cgu_div_info {
	unsigned reg;
	u8 shift;
	u8 div;
	u8 bits;
	s8 ce_bit;
	s8 busy_bit;
	s8 stop_bit;
	u8 bypass_mask;
	const u8 *div_table;
};

/**
 * struct ingenic_cgu_fixdiv_info - information about a fixed divider
 * @div: the divider applied to the parent clock
 */
struct ingenic_cgu_fixdiv_info {
	unsigned div;
};

/**
 * struct ingenic_cgu_gate_info - information about a clock gate
 * @reg: offset of the gate control register within the CGU
 * @bit: offset of the bit in the register that controls the gate
 * @clear_to_gate: if set, the clock is gated when the bit is cleared
 * @delay_us: delay in microseconds after which the clock is considered stable
 */
struct ingenic_cgu_gate_info {
	unsigned reg;
	u8 bit;
	bool clear_to_gate;
	u16 delay_us;
};

/**
 * struct ingenic_cgu_custom_info - information about a custom (SoC) clock
 * @clk_ops: custom clock operation callbacks
 */
struct ingenic_cgu_custom_info {
	const struct clk_ops *clk_ops;
};

Annotation

Implementation Notes