drivers/clk/ingenic/jz4755-cgu.c

Source file repositories/reference/linux-study-clean/drivers/clk/ingenic/jz4755-cgu.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/ingenic/jz4755-cgu.c
Extension
.c
Size
7497 bytes
Lines
347
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Ingenic JZ4755 SoC CGU driver
 * Heavily based on JZ4725b CGU driver
 *
 * Copyright (C) 2022 Siarhei Volkau
 * Author: Siarhei Volkau <lis8215@gmail.com>
 */

#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/of.h>

#include <dt-bindings/clock/ingenic,jz4755-cgu.h>

#include "cgu.h"
#include "pm.h"

/* CGU register offsets */
#define CGU_REG_CPCCR		0x00
#define CGU_REG_CPPCR		0x10
#define CGU_REG_CLKGR		0x20
#define CGU_REG_OPCR		0x24
#define CGU_REG_I2SCDR		0x60
#define CGU_REG_LPCDR		0x64
#define CGU_REG_MSCCDR		0x68
#define CGU_REG_SSICDR		0x74
#define CGU_REG_CIMCDR		0x7C

static struct ingenic_cgu *cgu;

static const s8 pll_od_encoding[4] = {
	0x0, 0x1, -1, 0x3,
};

static const u8 jz4755_cgu_cpccr_div_table[] = {
	1, 2, 3, 4, 6, 8,
};

static const u8 jz4755_cgu_pll_half_div_table[] = {
	2, 1,
};

static const struct ingenic_cgu_clk_info jz4755_cgu_clocks[] = {

	/* External clocks */

	[JZ4755_CLK_EXT] = { "ext", CGU_CLK_EXT },
	[JZ4755_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT },

	[JZ4755_CLK_PLL] = {
		"pll", CGU_CLK_PLL,
		.parents = { JZ4755_CLK_EXT, },
		.pll = {
			.reg = CGU_REG_CPPCR,
			.rate_multiplier = 1,
			.m_shift = 23,
			.m_bits = 9,
			.m_offset = 2,
			.n_shift = 18,
			.n_bits = 5,
			.n_offset = 2,
			.od_shift = 16,
			.od_bits = 2,
			.od_max = 4,
			.od_encoding = pll_od_encoding,
			.stable_bit = 10,
			.bypass_reg = CGU_REG_CPPCR,
			.bypass_bit = 9,
			.enable_bit = 8,
		},
	},

	/* Muxes & dividers */

	[JZ4755_CLK_PLL_HALF] = {
		"pll half", CGU_CLK_DIV,
		.parents = { JZ4755_CLK_PLL, },
		.div = {
			CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0,
			jz4755_cgu_pll_half_div_table,
		},
	},

	[JZ4755_CLK_EXT_HALF] = {
		"ext half", CGU_CLK_DIV,
		.parents = { JZ4755_CLK_EXT, },
		.div = {
			CGU_REG_CPCCR, 30, 1, 1, -1, -1, -1, 0,
			NULL,

Annotation

Implementation Notes