drivers/clk/ingenic/jz4760-cgu.c

Source file repositories/reference/linux-study-clean/drivers/clk/ingenic/jz4760-cgu.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/ingenic/jz4760-cgu.c
Extension
.c
Size
11068 bytes
Lines
447
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * JZ4760 SoC CGU driver
 * Copyright 2018, Paul Cercueil <paul@crapouillou.net>
 */

#include <linux/bitops.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of.h>

#include <linux/clk.h>

#include <dt-bindings/clock/ingenic,jz4760-cgu.h>

#include "cgu.h"
#include "pm.h"

#define MHZ (1000 * 1000)

/*
 * CPM registers offset address definition
 */
#define CGU_REG_CPCCR		0x00
#define CGU_REG_LCR		0x04
#define CGU_REG_CPPCR0		0x10
#define CGU_REG_CLKGR0		0x20
#define CGU_REG_OPCR		0x24
#define CGU_REG_CLKGR1		0x28
#define CGU_REG_CPPCR1		0x30
#define CGU_REG_USBPCR		0x3c
#define CGU_REG_USBCDR		0x50
#define CGU_REG_I2SCDR		0x60
#define CGU_REG_LPCDR		0x64
#define CGU_REG_MSCCDR		0x68
#define CGU_REG_UHCCDR		0x6c
#define CGU_REG_SSICDR		0x74
#define CGU_REG_CIMCDR		0x7c
#define CGU_REG_GPSCDR		0x80
#define CGU_REG_PCMCDR		0x84
#define CGU_REG_GPUCDR		0x88

static const s8 pll_od_encoding[8] = {
	0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
};

static const u8 jz4760_cgu_cpccr_div_table[] = {
	1, 2, 3, 4, 6, 8,
};

static const u8 jz4760_cgu_pll_half_div_table[] = {
	2, 1,
};

static void
jz4760_cgu_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info,
		       unsigned long rate, unsigned long parent_rate,
		       unsigned int *pm, unsigned int *pn, unsigned int *pod)
{
	unsigned int m, n, od, m_max = (1 << pll_info->m_bits) - 1;

	/* The frequency after the N divider must be between 1 and 50 MHz. */
	n = parent_rate / (1 * MHZ);

	/* The N divider must be >= 2. */
	n = clamp_val(n, 2, 1 << pll_info->n_bits);

	rate /= MHZ;
	parent_rate /= MHZ;

	for (m = m_max; m >= m_max && n >= 2; n--) {
		m = rate * n / parent_rate;
		od = m & 1;
		m <<= od;
	}

	*pm = m;
	*pn = n + 1;
	*pod = 1 << od;
}

static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = {

	/* External clocks */

	[JZ4760_CLK_EXT] = { "ext", CGU_CLK_EXT },
	[JZ4760_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT },

	/* PLLs */

Annotation

Implementation Notes